Agilent Technologies 1680, 1690 manual Acquisition Board Self Tests

Chapter 8: Theory of Operation

Self-Tests Descriptions

Acquisition Board Self Tests

The acquisition board self tests are available in the Agilent Logic Analyzer application software user interface. These self tests verify the correct operation of the acquisition board in both the Agilent 1680A,AD-series and 1690A,AD- series logic analyzers

Register Test. The Register Test verifies that the registers of each acquisition IC are operating properly. Test patterns are written to each register on each acquisition IC, read, and compared with known values. The registers are reset, and verified that each register has been initialized. Test patterns are then written to ensure the chip address lines are not shorted or opened. Finally test data is written to registers of individual acquisition ICs to ensure each acquisition IC can be selected independently.

Passing the Register Test implies that the acquisition IC registers can store acquisition control data to properly manage the operating of each IC.

Memory Test. The Memory Test verifies that each bit in the acquisition memory IC can be written with a logic “0” and logic “1” through the Serial Access Memory port. Test data is generated using a shifting test register in the acquisition ICs.

The serialized test patterns are then sent to the memory port of each acquisition memory IC and stored. The data in the acquisition memory ICs are then downloaded and compared with known values.

Passing the Memory Test implies the acquisition memory can store data written through the memory port. This test along with the Memory Modes Test provides complete testing of the memory ICs.

Comparator Test. The Comparator Test ensures the data signal comparators in the module front end can be set to their maximum and minimum thresholds and that they recognize activity at the signal inputs. A clock signal is routed to a test port on each comparator. The threshold is then set to the minimum value. The comparator output is then read and compared with a known value. The threshold is then set to a maximum value. The comparator output is again read and compared with a known value.

Passing the Comparators Test implies that the front-end comparators are operating properly, can recognize both a logic ì0î and logic ì1î, and can properly send the acquisition data downstream to the acquisition ICs.

Trigger Bus Test. The Trigger Bus Test verifies the trigger resource lines that run between each acquisition IC. The test ensures that the trigger resource lines can be both driven as outputs and read as inputs. The resource registers are written with test patterns, read back, then compared with known values. The resource registers are then written with test patterns, read back from a different acquisition IC, then compared with known values.

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