Agilent Technologies 1680, 1690 Check the setup/hold with single clock edges, multiple clocks

Chapter 3: Testing Performance

To test the multiple-clock state acquisition

bOn the oscilloscope, select [Shift] + width: channel 1, then select [Enter] to display the data signal pulse width (+ width (1)).

cIf the pulse width is outside the limits, adjust the pulse generator channel 2 width until the pulse width is within limits.

Check the setup/hold with single clock edges, multiple clocks

The following setup/hold combinations will be tested.

Setup/Hold Combinations

Test	Setup/Hold	Setup/Hold	Sample Position
Combination	Times	Window	(in middle of Window)
1	5.0/-2.0 ns	3.0 ns	-3.5 ns
2	-1.5/4.50 ns	3.0 ns	+3.0 ns

1Disable the pulse generator channel 1 COMP (LED off).

2Using the Delay mode of the pulse generator channel 1, position the pulses

according to the setup time of the setup/hold combination selected,

+0.0 ps or −100 ps as measured on the oscilloscope:

a On the Oscilloscope, select [Define meas] Define ∆ Time - Stop edge: rising, Edge number 2.

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