Chapter 2
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•Unified cache— Instruction cache and data cache are combined. For example, a processor may have primary cache with separate instruction and data cache memory, but unified secondary cache.
NPE-175 and NPE-225 Memory Information
To determine the memory configuration of your NPE, use the show version command.
The following example shows an
router(boot)# show version
Cisco Internetwork Operating System Software
IOS (tm) 7200 Software
Copyright (c)
Image
(display text omitted)
cisco 7206VXR (NPE225) processor with 57344K/8192K bytes of memory. R527x CPU at 262Mhz, Implementation 40, Rev 10.0, 2048KB L2 Cache 6 slot VXR midplane, Version 2.0
(display text omitted)
Table
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Memory Type |
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SDRAM |
| 64 or 128 MB | 1 configurable | DIMM | U15 |
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| bank with 1 |
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| SDRAM slot |
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Boot ROM |
| 512 KB | 1 | OTP ROM for the ROM monitor | U1 |
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| program |
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Primary cache |
| 16 KB (instruction), | — | RM5270 processor, primary internal | U4 |
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| 16 KB (data) |
| cache |
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| 32 KB (instruction), | — | RM5271 processor, primary internal | U4 |
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| 32 KB (data) |
| cache |
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Secondary cache | 2 MB | 4 x 256 x 18 bits = | RM527x processor, unified external | U5, U6, U7, U81 | |
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| 64 bit plus 4 parity | cache |
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1. Located on the processor engine board.
Network Processing Engine and Network Services Engine Installation and Configuration
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