Cisco Systems Cisco 12008 manual Overview of the Cisco

Overview of the Cisco 12008

Each OC-12c/STM-4c ATM line card incorporates the following primary components:

•Reassembly and segmentation—The transceivers support packet reassembly (converting ATM cells to packets) and segmentation (converting packets to ATM cells). The transceivers can handle up to 4000 simultaneous reassemblies (based on an average packet size of 280 bytes). In addition, the reassembly application-specific integrated circuit (ASIC) and the segmentation ASIC support up to 15,000 active virtual circuits.

The SONET specification for fiber-optic transmission defines two types of fiber: single mode and multimode. Signals can travel farther through single mode fiber than through multimode fiber.

The maximum distance for single-mode installations is determined by the amount of light loss in the fiber path. Good quality single-mode fiber with very few splices can carry an OC-3c/STM-1c signal 9.3 miles (15 km) or more; good quality miltimode fiber can carry a signal up to 1640 feet (500 m).

•Burst buffers—The burst buffer (4 MB) prevents the dropping of packets during instantaneous increases in the number of back-to-back small packets being transmitted at OC-12 line rates. Burst buffers provide high throughput while smoothing out the arriving packet burst for the Layer 3 switch processor.

•Buffer memory—The silicon queuing engine controls the placement of IP packets in buffer memory as well as their removal from buffer memory. The default packet buffer memory is 32 MB, which includes 16 MB of receive (Rx) buffers and 16 MB of transmit (Tx) buffers. The buffer memory can be configured to support up to 64 MB of receive buffers and 64 MB of transmit buffers. The buffers can support delays comparable to the longest round trip delays measured in the Internet at OC-3/STM-1 line rates.

•Layer 2 switching accelerator—The Layer 2 switching accelerator assists the forwarding processor. It is a specially designed application-specific integrated circuit (ASIC) that optimizes access to the Layer 2 and Layer 3 information within each packet. At very high line rates, this access process must be executed as rapidly as possible, which is why an ASIC is dedicated to the process.

•Forwarding processor—A forwarding processor makes forwarding decisions based on information in the Cisco Express Forwarding (CEF) table and the Layer 2 and Layer 3 information in the packet. The GRP constantly updates forwarding information in the forwarding table based on the latest information in the routing table.

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