Overview of the Cisco 12008
Once the forwarding decision has been made, the silicon queuing engine is notified by the forwarding processor, and the silicon queuing engine places the packet in the proper queue.
This partitioning between the Layer 2 switching accelerator and the forwarding processor blends the high throughput of
•Silicon queuing
When an incoming IP packet is clocked into the silicon queuing engine, the packet’s integrity is verified by a CRC check. Next, the silicon queuing engine transfers the IP packet to buffer memory and tells the Layer 3 switching accelerator the location of the IP packet. Simultaneously, the silicon queuing engine is receiving forwarding information from the forwarding processor, while the forwarding processor is telling the silicon queuing engine where the IP packet is to be placed in the virtual output queue.
Each virtual output queue represents an output destination (destination line card). Placement of the IP packets in a virtual output queue is based on the decision made by the forwarding processor. There is one virtual output queue for each line card, plus a dedicated virtual output queue for multicast service.
The transmit silicon queuing engine moves the packet from the switch fabric to the transmit buffer, and then to the transmit interface.
•Switch fabric
•Maintenance bus (MBus)
In addition, the MBus module on the line card contains the
•Cisco Express Forwarding (CEF) memory
