Overview of the Cisco 12008
Cisco 12008 Gigabit Switch Router Installation and Configuration Guide
1-58
Each Quad OC-3c/STM-1c POS line card incorporates the following major components:
•Transceivers—The single-mode intermediate reach transceiver provides a full-duplex,
155-Mbps, 1300-nm, laser-based SONET/SDH-compliant interface. The multimode
transceiver provides a full-duplex, 155-Mbps, 1300-nm, LED-based SONET/SDH
compliant interface.
The SONET specification for fiber-optic transmission defines two types of fiber: single
mode and multimode. Signals can travel farther through single mode fiber than through
multimode fiber.
The maximum distance for single-mode installations is determined by the amount of
light loss in the fiber path. Good quality single-mode fiber with very few splices can
carry an OC-3c/STM-1c signal 9.3 mi les (15 km) or more; good quality milti mode fiber
can carry a signal up to 1.3 miles (2 km).
•Burst buffers—The Quad-OC3c/STM-1c contains four 128-KB burst buffers. The b urst
buffer prevents the dropping of packets during instantaneous increases in the number of
back-to-back small packets being transmitted at OC-3 line rates.
Burst buffers are used to achieve high throughput while smoothing out the arriving
packet burst for the Layer 3 switch processor.
•Buffer memory—The silicon queuing engine controls the placement of IP packets in
buffer memory as well as their removal from buffer memory. The default packet buffer
memory is 32 MB, which includes 16 MB of receive (Rx) buffers and 16 MB of transmit
(Tx) buffers.
The buffer memory can be configured to support up to 64 MB of receive buffers and up
to 64-MB of transmit buffers. The buffers can support delays comparable to the longest
round trip delays measured in the Internet at OC-3c/STM-1c line rates.
•Layer 2 switching accelerator—The Layer 2 switching accelerator assists the
forwarding processor. It is a specially designed application-specific integrated circuit
(ASIC) that optimizes access to the Layer 2 and Layer 3 information within each packet.
At very high line rates, this access process must be executed as rapidly as possible,
which is why an ASIC is dedicated to the process.
•Forwarding processor—A forwarding processor makes forwarding decisions based on
the information in the Cisco Express Forwarding (CEF) table and the Layer 2 and Layer
3 information in the packet. The GRP constantly updates forwarding information in the
forwarding table based on the latest information in the routing table.