Epson S1C33210 manual 123

APPENDIX B PIN CHARACTERISTICS

Pin No.		Signal name	I/O cell	Characteristic		Pull-up/	Power	Remarks
			name	Input	Output	down	supply
101		CTS	XIBC	CMOS/LVTTL			VDD
102		VSS
103		PLLC	XLIN				VDD
104		VSS	XIBCD1	CMOS/LVTTL		Pull-down
105		PLLS1	XIBC	CMOS/LVTTL			VDD
106		PLLS0	XIBC	CMOS/LVTTL			VDD
107		RXD/SIN3	XIBC	CMOS/LVTTL			VDD
108		DCD	XIBC	CMOS/LVTTL			VDD
109		MSEL	XIBCP2			Pull-up	VDD
110		GOUT	XOB1T	CMOS/LVTTL	2 mA		VDD
111		VDD
112		OSC3	XLIN				VDD
113		OSC4	XLOT				VDD
114		EA10MD0	XIBC	CMOS/LVTTL			VDD
115		EA10MD1	XIBCP2	CMOS/LVTTL		Pull-up	VDD
116		#X2SPD	XIBC	CMOS/LVTTL			VDD
117		P21/#DWE/#GAAS	XBH1T	CMOS/LVTTL SCHMITT	2 mA		VDD
118		P22/TM0	XBH1T	CMOS/LVTTL SCHMITT	2 mA		VDD
119		P23/TM1	XBH1T	CMOS/LVTTL SCHMITT	2 mA		VDD
120		DSIO	XBH2P2T	CMOS/LVTTL SCHMITT	6 mA	Pull-up	VDD
121		P10/EXCL0/T8UF0/DST0	XBH2T	CMOS/LVTTL SCHMITT	6 mA		VDD
122		P11/EXCL1/T8UF1/DST1	XBH2T	CMOS/LVTTL SCHMITT	6 mA		VDD
123		P12/EXCL2/T8UF2/DST2	XBH2T	CMOS/LVTTL SCHMITT	6 mA		VDD
124		P13/EXCL3/T8UF3/DPC0	XBH2T	CMOS/LVTTL SCHMITT	6 mA		VDD
125		P14/FOSC1/DCLK	XBH2T	CMOS/LVTTL SCHMITT	6 mA		VDD
126		P24/TM2/#SRDY2	XBH1T	CMOS/LVTTL SCHMITT	2 mA		VDD
127		P25/TM3/#SCLK2	XBH1T	CMOS/LVTTL SCHMITT	2 mA		VDD
128		P15/EXCL4/#DMAEND0	XBH1T	CMOS/LVTTL SCHMITT	2 mA		VDD
Note 1)	The voltage applied to this pin must be 0V ≤ VIN ≥ VDD.
Note 2)	This pin is set as an input pin during device testing. Normally it is an output pin.
Note 3)	The XBB1 cell is a fail-safe cell.

S1C33210 PRODUCT PART EPSON A-109