1 OUTLINE
Pin name | Pin No. | I/O |
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DTR | 95 | O | – | DTR output *1 | |
RTS | 94 | O | – | RTS output*1 |
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TXD | 100 | O | – | TXD: | TXD output*1 when MSEL pin input is at High level |
SOUT3 |
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| SOUT3: | SOUT3 output when MSEL pin input is at Low level |
RI | 97 | I | – | RI input *1 |
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CTS | 101 | I | – | CTS input *1 |
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DCD | 108 | I | – | DCD input *1 |
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DSR | 96 | I | – | DSR input *1 |
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RXD | 107 | I | – | RXD: | RXD input when MSEL pin input is at High level |
SIN3 |
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| SIN3: | SIN3 input when MSEL pin input is at Low level |
CNT1 | 99 | O | – | Mobile access control output #1 | |
CNT2 | 98 | O | – | Mobile access control output #2 | |
MSEL | 109 | I | Serial I/O interface Ch. 3 configuration input. Normally drive this at High level. | ||
GOUT | 110 | O | – | NMI interrupt request output |
Note: *1 The communications macro select (MCRS) register (D[1:0]/0x200000) configures the I/O signals to match the target mobile device.
Table 1.3.5 List of Pins for Clock Generator
Pin name | Pin No. | I/O |
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OSC1 | 51 | I | – | ||||||
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| input) |
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OSC2 | 50 | O | – |
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OSC3 | 112 | I | – | ||||||
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| input) |
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OSC4 | 113 | O | – |
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PLLS[1:0] | 105,106 | I | – | PLL |
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| PLLS1 | PLLS0 | fin (fOSC3) | fout (fPSCIN) |
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| 1 | 1 |
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| 0 | 1 |
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| 0 | 0 | PLL is not | L | ||
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| used |
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PLLC | 103 | – | – | Capasitor connecting pin for PLL |
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| Table 1.3.6 List of Other Pins |
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Pin name | Pin No. | I/O |
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| Function | |||
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| /down |
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TST | 80 | I | Pull- | Test mode input. This pin is used for testing this chip. For further details, refer | |||||
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| down | to the S1C33 ASIC Design Guide. |
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DSIO | 120 | I/O | Serial I/O pin for debugging |
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| This pin is used to communicate with the debugging tool S5U1C33000H. | |||||
#X2SPD | 116 | I | – | Clock | |||||
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| clock ⋅ 2 |
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#NMI | 44 | I | NMI request input pin |
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#RESET | 43 | I | Initial reset input pin |
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Note: "#" in the pin names indicates that the signal is low active.
EPSON | S1C33210 PRODUCT PART |