III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES

PDC Communications Mode

Overview

The PDC communications mode works in combination with the software modem module to process ARQ frames for data transfers with PDC devices.

For a transmit operation, this mode serially transmits 24 bytes of data from one of two buffers plus two 16-bit CRCs using the frame and clock timing from the PDC device. For a receive operation, it receives 24 bytes of data and two 16-bit CRCs into one of two buffers, checks the CRCs, and stores the results in a register.

This mode sends interrupt requests to the CPU every 20 ms at the falling edge of the frame signal from the PDC device.

For communications macro select (MCRS) register (D[1:0]/0x200000) settings other than 00–that is, HDLC, PDC, and PHS communications modes–the MOPORT3 and MOPORT2 bits in the communications block output port data register (D[3:0]/0x020000A) drive the RTS and DTR pins using negative logic.

The MIPORT[1:0] bits in the communications block input port data register (D[1:0]/0x020000C) track the input levels for the DSR and RI pins.

Signal Format

Figure 10.7 summarizes the serial data signal format for PDC communications.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20 ms

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Transmit interval

 

 

 

 

 

 

 

 

 

 

Receive interval

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DCD (PDC frame signal)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TXD (Transmit serial output)

 

 

Transmit data

 

 

(224 bits)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RXD (Receive serial input)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(224 bits)

 

Receive data

 

 

 

CTS (PDC clock)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(Total 224 bits)

TXD and RXD (shared)

 

 

0

1

2

3

4

5

6

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 10.7 PDC Communications Data Format

Data Buffers

PDC communications uses two 32-byte buffers each for transmitting and receiving. Transmitoperation usesonly the 24 bytes at the start of a buffer; receive operation, 28.

The transmit buffers are write only; the receive buffers, read only.

Although the device size is eight bytes, all reads and writes are in halfwords, so use only even addresses as shown in the next Figure.

B-III-10-8

EPSON

S1C33210 FUNCTION PART