III PERIPHERAL BLOCK: LOW-SPEED (OSC1) OSCILLATION CIRCUIT

The following shows the operating status in HALT mode (basic mode and HALT2 mode) and SLEEP mode.

Table 6.4 Operating Status in Standby Mode

Standby mode

 

Operating status

 

Reactivating factor

HALT mode

Basic mode

•

The CPU clock is stopped. (CPU stop status)

•

Reset, NMI

 

 

•

BCU clock is supplied. (BCU run status)

•

Enabled (not masked) interrupt

 

 

•

DMA clock is not stopped. (DMA run status)

 

factors

 

 

• Clocks for the peripheral circuits maintain the

 

 

 

 

 

status before entering HALT mode. (run or

 

 

 

 

 

stop)

 

 

 

 

• The high-speed oscillation circuit maintains

 

 

 

 

 

the status before entering HALT mode.

 

 

 

 

• The low-speed oscillation circuit maintains the

 

 

 

 

 

status before entering HALT mode.

 

 

 

HALT2 mode

•

The CPU clock is stopped. (CPU stop status)

In HALT2 mode, operation can be

 

 

•

BCU clock is stopped. (BCU stop status)

restarted by the following events.

 

 

•

DMA clock is stopped. (DMA stop status)

•

Reset, NMI

 

 

•

Clocks for the peripheral circuits maintain the

• The occurrence of an unmasked

 

 

 

status before entering HALT mode. (run or

 

interrupt

 

 

 

stop)

However, interrupts from peripheral

 

 

•

The high-speed oscillation circuit maintains

circuits require that the clock

 

 

 

the status before entering HALT mode.

supplied to the peripheral circuit in

 

 

• The low-speed oscillation circuit maintains the

question be operating.

 

 

 

status before entering HALT mode.

 

 

SLEEP mode

•

The CPU clock is stopped. (CPU stop status)

•

Reset, NMI

 

 

•

BCU clock is stopped. (BCU stop status)

•

Enabled (not masked) input port

 

 

•

Clocks for the peripheral circuits are stopped.

 

interrupt factors

 

 

•

The high-speed oscillation circuit is stopped.

•

Clock timer interrupt when the

 

 

•

The low-speed oscillation circuit maintains the

 

low-speed oscillation circuit is

 

 

 

status before entering SLEEP mode.

 

being operated

PF1ON: OSC1 external output control (D0) / Clock option register (0x40190)

Turns the low-speed (OSC1) clock output to external devices on or off.

Write "1": On

Write "0": Off

Read: Valid

The low-speed (OSC1) clock is output from the FOSC1 pin to an external device by writing "1" to PF1ON. However, for this setting to be effective, the P14 pin must be set for the FOSC1 pin by CFP14 and CFEX0, and output must be set by setting IOC14 (D4/0x402D6 <P1 I/O control register>) to "1".

The clock output is disabled by writing "0".

Writing to PF1ON is allowed only when CLGP[7:0] is set to "0b10010110". At initial reset, PF1ON is set to "0" (Off).

CLGP7–CLGP0:Power-control register protection flag ([D[7:0]) / Power control protection register (0x4019E)

These bits remove the protection against writing to addresses 0x40180 and 0x40190.

Write "0b10010110": Write protection removed

Write other than the above: No operation (write-protected)

Read: Valid

Before writing to address 0x40180 or 0x40190, set CLGP[7:0] to "0b10010110" to remove the protection against writing to that address. This clearing of write protection is effective for only one writing, so the bits are cleared to "0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to.

At initial reset, CLGP is set to "0b00000000" (write-protected).

S1C33210 FUNCTION PART

EPSON

B-III-6-7