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| 4 | PERIPHERAL CIRCUITS | |||
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Register name | Address | Bit | Name | Function |
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| Setting |
| Init. | R/W | Remarks |
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Areas | 004812A | – | reserved |
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| – |
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| – | – | 0 when being read. |
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(HW) | DD | A6DF1 | Area 6 | A6DF[1:0] |
| Number of cycles | 1 | R/W |
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| DC | A6DF0 | output disable delay time | 1 |
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| 1 |
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| 3.5 | 1 |
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| 1 |
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| 0 |
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| 2.5 |
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| 0 |
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| 1 |
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| 1.5 |
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| 0 |
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| 0 |
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| 0.5 |
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| DB | – | reserved |
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| – |
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| – | – | 0 when being read. |
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| DA | A6WT2 | Area 6 wait control | A6WT[2:0] |
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| Wait cycles | 1 | R/W |
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| D9 | A6WT1 |
| 1 |
| 1 | 1 |
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| 7 | 1 |
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| D8 | A6WT0 |
| 1 |
| 1 | 0 |
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| 6 | 1 |
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| 1 |
| 0 | 1 |
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| 5 |
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| 1 |
| 0 | 0 |
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| 4 |
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| 0 |
| 1 | 1 |
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| 3 |
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| 0 |
| 1 | 0 |
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| 2 |
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| 0 |
| 0 | 1 |
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| 1 |
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| 0 |
| 0 | 0 |
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| 0 |
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| D7 | – | reserved |
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| – |
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| – | – | 0 when being read. |
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| D6 | A5SZ | Areas | 1 | 8 bits |
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| 0 | 16 bits | 0 | R/W |
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| D5 | A5DF1 | Areas | A5DF[1:0] |
| Number of cycles | 1 | R/W |
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| D4 | A5DF0 | output disable delay time | 1 |
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| 1 |
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| 3.5 | 1 |
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| 1 |
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| 0 |
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| 2.5 |
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| 0 |
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| 1 |
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| 1.5 |
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| 0 |
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| 0 |
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| 0.5 |
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| D3 | – | reserved |
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| – | – | 0 when being read. |
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| D2 | A5WT2 | Areas | A5WT[2:0] |
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| Wait cycles | 1 | R/W |
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| D1 | A5WT1 |
| 1 |
| 1 | 1 |
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| 7 | 1 |
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| D0 | A5WT0 |
| 1 |
| 1 | 0 |
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| 6 | 1 |
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| 1 |
| 0 | 1 |
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| 5 |
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| 1 |
| 0 | 0 |
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| 4 |
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| 0 |
| 1 | 1 |
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| 3 |
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| 0 |
| 1 | 0 |
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| 2 |
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| 0 |
| 0 | 1 |
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| 1 |
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| 0 |
| 0 | 0 |
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| 0 |
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TTBR write | 004812D | D7 | TBRP7 | TTBR register write protect | Writing 01011001(0x59) | 0 | W | Undefined in read. |
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protect register | (B) | D6 | TBRP6 |
| removes the TTBR (0x48134) | 0 |
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| D5 | TBRP5 |
| write protection. |
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| 0 |
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| D4 | TBRP4 |
| Writing other data sets the | 0 |
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| D3 | TBRP3 |
| write protection. |
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| 0 |
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| D2 | TBRP2 |
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| 0 |
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| D1 | TBRP1 |
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| 0 |
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| D0 | TBRP0 |
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| 0 |
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Bus control | 004812E | DF | RBCLK | BCLK output control | 1 | Fixed at H |
| 0 | Enabled | 0 | R/W |
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register | (HW) | DE | – | reserved |
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| – |
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| 0 | – | Writing 1 not allowed. |
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| DD | RBST8 | Burst ROM burst mode selection | 1 |
| 0 | 0 | R/W |
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| DC | REDO | DRAM page mode selection | 1 | EDO |
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| 0 | Fast page | 0 | R/W |
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| DB | RCA1 | Column address size selection | RCA[1:0] |
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| Size | 0 | R/W |
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| DA | RCA0 |
| 1 |
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| 1 |
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| 11 | 0 |
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| 1 |
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| 0 |
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| 10 |
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| 0 |
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| 1 |
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| 9 |
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| 0 |
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| 0 |
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| 8 |
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| D9 | RPC2 | Refresh enable | 1 | Enabled |
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| 0 | Disabled | 0 | R/W |
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| D8 | RPC1 | Refresh method selection | 1 |
| 0 | 0 | R/W |
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| D7 | RPC0 | Refresh RPC delay setup | 1 | 2.0 |
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| 0 | 1.0 | 0 | R/W |
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| D6 | RRA1 | Refresh RAS pulse width | RRA[1:0] |
| Number of cycles | 0 | R/W |
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| D5 | RRA0 | selection | 1 |
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| 1 |
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| 5 | 0 |
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| 1 |
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| 0 |
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| 4 |
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| 0 |
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| 1 |
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| 3 |
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| 0 |
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| 0 |
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| 2 |
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| D4 | – | reserved |
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| – |
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| 0 | – | Writing 1 not allowed. |
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| D3 | SBUSST | External interface method selection | 1 | #BSL |
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| 0 | A0 | 0 | R/W |
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| D2 | SEMAS | External bus master setup | 1 | Existing |
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| 0 | Nonexistent | 0 | R/W |
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| D1 | SEPD | External | 1 | Enabled |
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| 0 | Disabled | 0 | R/W |
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| D0 | SWAITE | #WAIT enable | 1 | Enabled |
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| 0 | Disabled | 0 | R/W |
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S1C33210 PRODUCT PART | EPSON |