III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
Register name | Address | Bit | Name | Function |
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| Setting |
| Init. | R/W | Remarks | ||||
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PHS receive | 0200206 | – | – |
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| – |
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| – | – | 0 when being read. | ||
status register | (HW) | D7 | RXINT | PHS receive interrupt flag | 1 | Request pending |
| 0 |
| No interrupts | 0 | R/W | Write "1" to clear | ||||
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| – | – |
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| – |
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| – | – | 0 when being read. | ||
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| D2 | CRCER | PHS receive data | 1 | CRC error |
| 0 |
| No error | X | R |
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| D1 | RXBS | PHS receive buffer select | 1 | Buffer B |
| 0 |
| Buffer A | X | R |
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| D0 | – | – |
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| – |
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| – | – | 0 when being read. | |
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HDLC interrupt | 0200302 | – | – |
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| – |
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| – | – | 0 when being read. | ||
control register | (HW) | D7 | ERES | HDLC error reset | 1 | Reset |
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| 0 |
| Ignored | 0 | W |
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| D6 | RESINT | HDLC reset E/S INT | 1 | Reset |
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| 0 |
| Ignored | 0 | W |
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| – | – |
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| – |
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| – | – | 0 when being read. | ||
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| D1 | RRXINT | HDLC reset Rx INT | 1 | Reset |
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| 0 |
| Ignored | 0 | W |
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| D0 | RTXINT | HDLC reset Tx INT | 1 | Reset |
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| 0 |
| Ignored | 0 | W |
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HDLC interrupt | 0200304 | – | – |
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| – |
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| – | – | 0 when being read. | ||
enable settings | (HW) | D7 | ABRTIES | HDLC enable bit for Abort | 1 | Enable |
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| 0 |
| Disabled | 0 | R/W | Writes of "0" are ignored | ||
register |
| D6 | TXUEIES | HDLC enable bit for Tx underrun/EOM | 1 | Enable |
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| 0 |
| Disabled | 0 | R/W | Writes of "0" are ignored | ||
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| D5 | HUNTIES | HDLC enable bit for Hunt | 1 | Enable |
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| 0 |
| Disabled | 0 | R/W | Writes of "0" are ignored | ||
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| D4 | IDLDIES | HDLC enable bit for idle detect | 1 | Enable |
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| 0 |
| Disabled | 0 | R/W | Writes of "0" are ignored | ||
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| conditions |
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| – | – |
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| – |
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| – | – | 0 when being read. | ||
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HDLC clear | 0200306 | – | – |
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| – |
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| – | – | 0 when being read. | ||
interrupt | (HW) | D7 | ABRTIEC | HDLC clear enable bit for Abort | 1 | Clear interrupt | 0 |
| Ignored | 0 | R/W |
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enable register |
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| enable |
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| D6 | TXUEIEC | HDLC clear enable bit for Tx | 1 | Clear interrupt | 0 |
| Ignored | 0 | R/W |
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| underrun/EOM |
| enable |
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| D5 | HUNTIEC | HDLC clear enable bit for Hunt | 1 | Clear interrupt | 0 |
| Ignored | 0 | R/W |
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| enable |
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| D4 | IDLDIEC | HDLC clear enable bit for idle | 1 | Clear interrupt | 0 |
| Ignored | 0 | R/W |
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| detect conditions |
| enable |
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| – | – | – |
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| – | – | 0 when being read. | |
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HDLC transfer | 0200308 | – | – |
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| – |
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| – | – | 0 when being read. | ||
settings | (HW) | D7 | RXENS | HDLC receive enable | 1 | Enable |
| 0 |
| Disable | 0 | R/W | Writes of "0" are ignored | ||||
register |
| D6 | TXENS | HDLC transmit enable | 1 | Enable |
| 0 |
| Disable | 0 | R/W | Writes of "0" are ignored | ||||
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| – | – |
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| – |
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| – | – | 0 when being read. | ||
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| D1 | RXIES | HDLC Rx and Sp INT enable | 1 | Enable |
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| 0 |
| Disabled | 0 | R/W | Writes of "0" are ignored | ||
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| D0 | TXIES | HDLC Tx INT enable | 1 | Enable |
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| 0 |
| Disabled | 0 | R/W | Writes of "0" are ignored | ||
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HDLC cancel | 020030A | – | – |
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| – |
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| – | – | 0 when being read. | ||
transfer | (HW) | D7 | RXENC | HDLC clear receive enable | 1 | Clear enable |
| 0 |
| Ignored | 0 | R/W |
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register |
| D6 | TXENC | HDLC clear transmit enable | 1 | Clear enable |
| 0 |
| Ignored | 0 | R/W |
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| – | – |
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| – |
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| – | – | 0 when being read. | ||
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| D1 | RXIEC | HDLC clear Rx and Sp INT enable | 1 | Clear enable |
| 0 |
| Ignored | 0 | R/W |
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| D0 | TXIEC | HDLC clear Tx INT enable | 1 | Clear enable |
| 0 |
| Ignored | 0 | R/W |
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HDLC receive | 020030C | – | – |
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| – |
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| – | – | 0 when being read. | ||
address | (HW) | D7 | RXADD7 | HDLC receive address |
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| 0x00 to 0xFF | 0 | R/W |
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register |
| D6 | RXADD6 | RXADD7 = MSB |
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| 0 |
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| D5 | RXADD5 | RXADD0 = LSB |
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| 0 |
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| D4 | RXADD4 |
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| 0 |
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| D3 | RXADD3 |
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| 0 |
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| D2 | RXADD2 |
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| 0 |
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| D1 | RXADD1 |
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| 0 |
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| D0 | RXADD0 |
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| 0 |
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HDLC receive | 020030E | – | – |
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| – |
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| – | – | 0 when being read. | ||
operation | (HW) | D7 | ADDCE | HDLC address compare enable | 1 | Enable |
| 0 |
| Disable | 0 | R/W |
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settings |
| D6 | ADDCM | HDLC address compare mode | 1 | Half |
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| 0 |
| Full | 0 | R/W |
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register |
| D5 | IDLDE | HDLC idle detect enable | 1 | Enable |
| 0 |
| Disable | 0 | R/W |
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| D4 | SHFDE | HDLC short frame detect enable | 1 | Enable |
| 0 |
| Disable | 0 | R/W |
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| – | – |
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| – |
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| – | – | 0 when being read. | ||
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HDLC receive | 0200310 | – | – |
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| – |
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| – | – | 0 when being read. | ||
queue interrupt | (HW) | D2 | RXFTH2 | HDLC receive queue interrupt | RXFTH[2:0] |
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| Level | 0 | R/W |
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threshold |
| D1 | RXFTH1 | threshold | 1 |
| 1 |
| 1 |
| 8 (Full) | 0 | R/W |
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register |
| D0 | RXFTH0 |
| 1 |
| 1 |
| 0 |
| 7 |
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| 0 | R/W |
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| 1 |
| 0 |
| 1 |
| 6 |
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| 1 |
| 0 |
| 0 |
| 5 |
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| 0 |
| 1 |
| 1 |
| 4 (Half) |
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| 0 |
| 1 |
| 0 |
| 3 |
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| 0 |
| 0 |
| 1 |
| 2 |
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| 0 |
| 0 |
| 0 |
| 1 (receive |
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| character available) |
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S1C33210 FUNCTION PART | EPSON |