III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

SELFM0: Timer 0 fine mode selection (D6) / 16-bit timer 0 control register (0x48186)

SELFM1: Timer 1 fine mode selection (D6) / 16-bit timer 1 control register (0x4818E)

SELFM2: Timer 2 fine mode selection (D6) / 16-bit timer 2 control register (0x48196)

SELFM3: Timer 3 fine mode selection (D6) / 16-bit timer 3 control register (0x4819E)

SELFM4: Timer 4 fine mode selection (D6) / 16-bit timer 4 control register (0x481A6)

SELFM5: Timer 5 fine mode selection (D6) / 16-bit timer 5 control register (0x481AE)

Sets fine mode for clock output.

Write "1": Fine mode

Write "0": Normal output

Read: Valid

When SELFMx is set to "1", clock output is set in fine mode which allows adjustment of the output signal duty ratio in units of a half cycle for the input clock.

When SELFMx is set to "0", normal clock output will be performed. At initial reset, SELCFMx is set to "0" (normal output).

SELCRB0: Timer 0 comparison register buffer enable (D5) / 16-bit timer 0 control register (0x48186)

SELCRB1: Timer 1 comparison register buffer enable (D5) / 16-bit timer 1 control register (0x4818E)

SELCRB2: Timer 2 comparison register buffer enable (D5) / 16-bit timer 2 control register (0x48196)

SELCRB3: Timer 3 comparison register buffer enable (D5) / 16-bit timer 3 control register (0x4819E)

SELCRB4: Timer 4 comparison register buffer enable (D5) / 16-bit timer 4 control register (0x481A6)

SELCRB5: Timer 5 comparison register buffer enable (D5) / 16-bit timer 5 control register (0x481AE)

Enables or disables writing to the comparison register buffer.

Write "1": Enabled

Write "0": Disabled

Read: Valid

When SELCRBx is set to "1", comparison data is read and written from/to the comparison register buffer. The content of the buffer is loaded to the comparison data register when the counter is reset by the software or the comparison B signal.

When SELCRBx is set to "0", comparison data is read and written from/to the comparison data register. At initial reset, SELCRBx is set to "0" (disabled).

OUTINV0: Timer 0 output inversion (D4) / 16-bit timer 0 control register (0x48186)

OUTINV1: Timer 1 output inversion (D4) / 16-bit timer 1 control register (0x4818E)

OUTINV2: Timer 2 output inversion (D4) / 16-bit timer 2 control register (0x48196)

OUTINV3: Timer 3 output inversion (D4) / 16-bit timer 3 control register (0x4819E)

OUTINV4: Timer 4 output inversion (D4) / 16-bit timer 4 control register (0x481A6)

OUTINV5: Timer 5 output inversion (D4) / 16-bit timer 5 control register (0x481AE)

Selects a logic of the output signal.

Write "1": Inverted (active low)

Write "0": Normal (active high)

Read: Valid

By writing "1" to OUTINVx, an active-low signal (off level = high) is generated for the TMx output. When OUTINVx is set to "0", an active-high signal (off level = low) is generated.

At initial reset, OUTINVx is set to "0" (active high).

B-III-4-20

EPSON

S1C33210 FUNCTION PART