III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
HDLC Communications Control and Operation
Transmit Control
(1)Enabling transmit operation
Setting the transmit enable (TXENS) bit in the HDLC command register (D6/0x0200308) to "1" enables transmit operation, starting transmission from the start of the specified transmit queue using the HDLC clock timing.
(2)Basic Procedure
Write the address, control, and data fields to the HDLC transmit data register (0x020031E).
The hardware automatically adds the CRC if the software writes "0" to the Tx underrun/EOM bit in the HDLC transmit status register (D7/0x0200334) before a Tx underrun. Otherwise, the hardware skips the CRC (or Abort) fields, sending the flag pattern immediately after the data field.
Specifying Abort with the CRC/Abort on underrun/EOM bit in the HDLC transmit operation settings register (D1/0x0200318) replaces the CRC field with an abort pattern (eight "1" bits).
Zero insertion applies from the address through FCS (CRC) fields, but not to the abort pattern replacing the CRC field.
(3)Ending transmit operation
To terminate transmit operation, write "1" to the send abort command bit in the HDLC transmit control register (D[6]/0x020031C) to send an abort pattern (eight "1" bits) followed by the specified idle pattern, mark or flag. The send abort command immediately terminates data transmission regardless of byte boundaries, sends the abort pattern, and clears the queue.
Writing "1" to the clear transmit enable bit in the HDLC transfer release register (D6/0x020030A) to disable transmit operation during a frame transmit operation also cancels transmit operation. The hardware immediately terminates transmission of the current byte, shifts to the transmit operation disabled state, and fixes the output at High level (mark state). Note that the queue data remains unchanged. Clearing it requires writing "1" to the reset transmit queue command bit in the HDLC transmit control register (D5/0x020031C). Either command immediately terminates data transmission regardless of byte boundaries.
(4)Transmit pattern for idle state
The output pattern is Mark (all "1") between a reset and an enable transmit command and after that command depends on the setting in the Mark/Flag on idle (MRKFLG) bit in the HDLC transmit operation settings register (D0/0x0200318).
Receive Control
(1)Enabling receive operation
Setting the receive enable (RXENS) bit in the HDLC transfer settings register (D7/0x0200308) to "1" enables receive operation, including detection of flag and abort patterns.
(2)Basic Procedure
After initialization and the enable receive command, the receive block starts hunting for the flag pattern. Detection of this pattern sets the Hunt bit in the HDLC E/S INT receive status register to "0" to indicate flag synchronization.
To
Note that the receive queue remains unchanged. Clearing it requires writing "1" to the reset receive queue command bit in the HDLC receive control register (D2/0x0200314).
Receiving an abort pattern (seven or more "1" bits) either during or after a frame receive operation also cancels flag synchronization and restarts hunting for the flag pattern.
The hardware stores all data between the opening and closing flag patterns in the receive queue.
(3)Establishing Receive Address
If the byte immediately following the opening flag pattern establishing flag synchronization is not a closing flag pattern, it is processed as the address field.
S1C33210 FUNCTION PART | EPSON |