Epson S1C33210 73

4

PERIPHERAL CIRCUITS

Register name

Address

Bit

Name

Function

Setting

Init.

R/W

Remarks

HDLC interrupt

0200302

D15–8

–

–

–

–

–

0 when being read.

control register

(HW)

D7

ERES

HDLC error reset

1

Reset

0

Ignored

0

W

D6

RESINT

HDLC E/S interrupt reset

1

Reset

0

Ignored

0

W

D5–2

–

–

–

–

–

0 when being read.

D1

RRXINT

HDLC receive interrupt reset

1

Reset

0

Ignored

0

W

D0

RTXINT

HDLC transmit interrupt reset

1

Reset

0

Ignored

0

W

HDLC interrupt

0200304

D15–8

–

–

–

–

–

0 when being read.

enable settings

(HW)

D7

ABRTIES

Enable Abort interrupt setting

1

Enable

0

Disabled

0

R/W

Writes of "0" are ignored

register

D6

TXUEIES

Enable TXUDR interrupt setting

1

Enable

0

Disabled

0

R/W

Writes of "0" are ignored

D5

HUNTIES

Enable Hunt interrupt setting

1

Enable

0

Disabled

0

R/W

Writes of "0" are ignored

D4

IDLDIES

Enable idle detection interrupt setting

1

Enable

0

Disabled

0

R/W

Writes of "0" are ignored

D3–0

–

–

–

–

–

0 when being read.

HDLC clear

0200306

D15–8

–

–

–

–

–

0 when being read.

interrupt

(HW)

D7

ABRTIEC

Clear Abort interrupt enable

1

Clear interrupt

0

Ignored

0

R/W

enable register

enable

D6

TXUEIEC

Clear TXUDR interrupt enable

1

Clear interrupt

0

Ignored

0

R/W

enable

D5

HUNTIEC

Clear Hunt interrupt enable

1

Clear interrupt

0

Ignored

0

R/W

enable

D4

IDLDIEC

Clear idle detection interrupt

1

Clear interrupt

0

Ignored

0

R/W

enable

enable

D3–0

–

–

–

–

–

0 when being read.

HDLC transfer

0200308

D15–8

–

–

–

–

–

0 when being read.

settings

(HW)

D7

RXENS

HDLC enable receive setting

1

Enable

0

Disable

0

R/W

Writes of "0" are ignored

register

D6

TXENS

HDLC enable transmit setting

1

Enable

0

Disable

0

R/W

Writes of "0" are ignored

D5–2

–

–

–

–

–

0 when being read.

D1

RXIES

HDLC enable receive interrupt setting

1

Enable

0

Disabled

0

R/W

Writes of "0" are ignored

D0

TXIES

HDLC enable transmit interrupt setting

1

Enable

0

Disabled

0

R/W

Writes of "0" are ignored

HDLC cancel

020030A

D15–8

–

–

–

–

–

0 when being read.

transfer

(HW)

D7

RXENC

HDLC clear receive enable

1

Clear enable

0

Ignored

0

R/W

register

D6

TXENC

HDLC clear transmit enable

1

Clear enable

0

Ignored

0

R/W

D5–2

–

–

–

–

–

0 when being read.

D1

RXIEC

HDLC clear receive interrupt enable

1

Clear enable

0

Ignored

0

R/W

D0

TXIEC

HDLC clear transmit interrupt enable

1

Clear enable

0

Ignored

0

R/W

HDLC receive

020030C

D15–8

–

–

–

–

–

0 when being read.

address

(HW)

D7

RXADD7

HDLC receive address

0x00 to 0xFF

0

R/W

register

D6

RXADD6

RXADD7 = MSB

0

D5

RXADD5

RXADD0 = LSB

0

D4

RXADD4

0

D3

RXADD3

0

D2

RXADD2

0

D1

RXADD1

0

D0

RXADD0

0

HDLC receive

020030E

D15–8

–

–

–

–

–

0 when being read.

operation

(HW)

D7

ADDCE

HDLC enable address compare

1

Enable

0

Disable

0

R/W

settings

D6

ADDCM

HDLC address compare mode

1

Half

0

Full

0

R/W

register

D5

IDLDE

HDLC enable idle detection

1

Enable

0

Disable

0

R/W

D4

SHFDE

HDLC enable short frame detection

1

Enable

0

Disable

0

R/W

D3–0

–

–

–

–

–

0 when being read.

HDLC receive

0200310

D15–3

–

–

–

–

–

0 when being read.

queue interrupt

(HW)

D2

RXFTH2

Receive queue interrupt level

RXFTH[2:0]

Level

0

R/W

threshold

D1

RXFTH1

1

1

1

8 (Full)

0

R/W

register

D0

RXFTH0

1

1

0

7

0

R/W

1

0

1

6

1

0

0

5

0

1

1

4 (Half)

0

1

0

3

0

0

1

2

0

0

0

1 (receive

character available)

S1C33210 PRODUCT PART

EPSON

A-59