
TABLE OF CONTENTS |
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| Bus Speed Mode ............................................................................................................................... | |
| Bus Clock Output............................................................................................................................... | |
| Bus Cycles in External System Interface ................................................................................................ | |
| SRAM Read Cycles........................................................................................................................... | |
| Bus Timing............................................................................................................................................ | |
| SRAM Write Cycles ........................................................................................................................... | |
| Burst ROM Read Cycles ................................................................................................................. | |
| DRAM Direct Interface.................................................................................................................................... | |
| Outline of DRAM Interface ............................................................................................................. | |
| DRAM Setting Conditions............................................................................................................... | |
| DRAM Read/Write Cycles............................................................................................................... | |
| DRAM Refresh Cycles ..................................................................................................................... | |
| Releasing External Bus ................................................................................................................................. | |
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| I/O Memory of BCU ......................................................................................................................................... | |
ITC (Interrupt Controller) ................................................................................. | ||
| Outline of Interrupt Functions......................................................................................................................... | |
| Maskable Interrupts............................................................................................................................. | |
| Interrupt Factors and Intelligent DMA........................................................................................... | |
| Nonmaskable Interrupt (NMI).......................................................................................................... | |
| Interrupt Processing by the CPU.................................................................................................... | |
| Clearing Standby Mode by Interrupts........................................................................................... | |
| Trap Table............................................................................................................................................................. | |
| Control of Maskable Interrupts ...................................................................................................................... | |
| Structure of the Interrupt Controller............................................................................................... | |
| Processor Status Register (PSR)................................................................................................... | |
| Interrupt Factor Flag and Interrupt Enable Register............................................................... | |
| Interrupt Priority Register and Interrupt Levels ......................................................................... | |
| IDMA Invocation.................................................................................................................................................. | |
| HSDMA Invocation........................................................................................................................................... | |
| I/O Memory of Interrupt Controller ............................................................................................................. | |
| Programming Notes......................................................................................................................................... | |
CLG (Clock Generator) .................................................................................... | ||
| Configuration of Clock Generator................................................................................................................. | |
| I/O Pins of Clock Generator ........................................................................................................................... | |
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| PLL ......................................................................................................................................................................... | |
| Controlling Oscillation....................................................................................................................................... | |
| Setting and Switching Over the CPU Operating Clock......................................................................... | |
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| Operation in Standby Mode ........................................................................................................................... | |
| I/O Memory of Clock Generator.................................................................................................................... | |
| Programming Notes........................................................................................................................................... | |
DBG (Debug Unit) ............................................................................................ | ||
| Debug Circuit........................................................................................................................................................ | |
| I/O Pins of Debug Circuit................................................................................................................................. |
iv | EPSON |