III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
If the enable bit in the HDLC receive operation settings register (D7/0x020030E) specifies address comparison, the hardware rejects frames whose address fields do not match the contents of the receive address register. Otherwise, it accepts them all.
If the address compare mode bit in the HDLC receive operation settings register (D6/0x020030E) specifies
(4)FCS (CRC) Check
The hardware retains the results of CRC checking from the end of the current frame through the start of the next. There is no command for clearing this status bit because the hardware automatically updates it at the end of each frame.
Note that errors do not trigger interrupt requests.
(5)Receiving Abort Pattern
An abort pattern is any sequence of seven or more "1" bits received while receive operation is enabled. One received during a receive operation immediately terminates the receive operation, cancels flag synchronization, and restarts hunting for the flag pattern. Because there may be data in the receive queue, clear it as necessary by writing "1" to the reset receive queue command bit in the HDLC receive control register (D2/0x0200314).
An abort pattern asserts the Abort bit in the HDLC E/S INT receive status register (D7/0x020032C), a trigger for the HDLC extra source status interrupt request (E/S INT). The return to the flag detection state also asserts the Hunt bit in the same register (D1/0x020032C), another trigger for that interrupt request.
(6)Suspending and Ending Receive Operation
Receiving a closing flag pattern without an intervening Abort pattern or other error constitutes successful completion of a frame receive operation.
A CRC error produces no special data processing. The hardware simply stores all data through the CRC in the receive queue.
An abort pattern, as already mentioned under (5) above, immediately terminates the receive operation, cancels flag synchronization, and restarts hunting for the flag pattern.
Writing "1" to the clear receive enable bit in the HDLC transfer release register (D7/0x020030A) to disable receive operation also immediately cancels receive operation. It also cancels flag synchronization, asserting the Hunt bit in the HDLC E/S INT receive status register (D1/0x020032C), a trigger for the HDLC extra source status interrupt request (E/S INT).
Because there may be data in the receive queue, read it or clear it as necessary by writing "1" to the reset receive queue command bit in the HDLC receive control register (D2/0x0200314).
Interrupt Outputs
HDLC communications uses four independent interrupts: HDLC transmit interrupt (Tx INT), HDLC receive interrupt (Rx INT), HDLC special condition (HDLC_SP) interrupt, and HDLC extra source status (HDLC_ES) interrupt.
All are level interrupts. They remain pending from the time that they are asserted until they are negated by the corresponding clear command.
(1)HDLC Transmit Interrupts (Tx INT)
There are no Tx INT interrupts between a reset and at least the first write of transmit data. Once transmit operation starts, however, there is one each time that the number of bytes in the transmit queue exceeds the setting in the HDLC transmit queue threshold register (D[1:0]/0x020031A). The only settings affecting Tx INT interrupts are this one and the Tx INT enable bit in the HDLC transmit settings register (D0/0x0200308). Writing more transmit data before the Tx underrun/EOM interrupt request flags in the HDLC E/S INT receive status (D5/0x020032C) and HDLC transmit status (D7/0x0200334) registers indicate the transmission of the second CRC byte produces a
EPSON | S1C33210 FUNCTION PART |