III PERIPHERAL BLOCK: SERIAL INTERFACE
Control and Operation of
Transmit control
(1)Enabling transmit operation
Use the
Ch.0
Ch.1
Ch.2
Ch.3
When transmit is enabled by writing "1" to this bit, the clock input to the shift register is enabled (ready for input), thus allowing for data to be transmitted. The synchronizing clock input/output of the #SCLKx pin is also enabled (ready for input/output).
Transmit is disabled by writing "0" to TXENx.
Note: Ch. 1 and Ch. 3 support only asynchronous operation.
After the function select register is set for the serial interface, the I/O direction of the #SRDY and #SCLK pins are changed at follows:
#SRDY: When slave mode is set, a switch is made to output mode. Otherwise, input mode is maintained.
#SCLK: When master mode is set, a switch is made to output mode. Otherwise, input mode is maintained.
Note: In
In addition, make sure TXENx is not set to "0" during a transmit operation.
(2)Transmit procedure
The serial interface contains a transmit shift register and a transmit data register (transmit data buffer), which are provided independently of those used for a receive operation.
Ch.0 transmit data: TXD0[7:0] (D[7:0]) / Serial I/F Ch.0 transmit data register (0x401E0)
Ch.1 transmit data: TXD1[7:0] (D[7:0]) / Serial I/F Ch.1 transmit data register (0x401E5)
Ch.2 transmit data: TXD2[7:0] (D[7:0]) / Serial I/F Ch.2 transmit data register (0x401F0)
Ch.3 transmit data: TXD3[7:0] (D[7:0]) / Serial I/F Ch.3 transmit data register (0x401F5) The serial interface contains a status bit to indicate the status of the transmit data register. Ch.0 transmit data buffer empty: TDBE0(D1) / Serial I/F Ch.0 status register (0x401E2)
Ch.1 transmit data buffer empty: TDBE1(D1) / Serial I/F Ch.1 status register (0x401E7)
Ch.2 transmit data buffer empty: TDBE2(D1) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 transmit data buffer empty: TDBE3(D1) / Serial I/F Ch.3 status register (0x401F7)
This bit is reset to "0" by writing data to the
The serial interface starts transmitting when data is written to the transmit data register.
The transfer status can be checked using the
Ch.0
Ch.1
Ch.2
Ch.3
This bit goes "1" when data is being transmitted and goes "0" when the transmission has completed.
When data is transmitted successively in
Following explains transmit operation in both the master and slave modes.
S1C33210 FUNCTION PART | EPSON |