III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES

Register name

Address

Bit

Name

Function

 

 

Setting

 

Init.

R/W

Remarks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Communications

0200026

D15–5

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

block CP3

(HW)

D4

CP3EN4

Assign UINT4 to CP3

 

1

Enable

0

 

Disable

0

R/W

CP3= CP3EN4*UINT4

interrupt select

 

D3

CP3EN3

Assign UINT3 to CP3

 

1

Enable

0

 

Disable

0

R/W

+CP3EN3*UINT3

register

 

D2

CP3EN2

Assign UINT2 to CP3

 

1

Enable

0

 

Disable

0

R/W

+CP3EN2*UINT2

 

 

D1

CP3EN1

Assign UINT1 to CP3

 

1

Enable

0

 

Disable

0

R/W

+CP3EN1*UINT1

 

 

D0

CP3EN0

Assign UINT0 to CP3

 

1

Enable

0

 

Disable

0

R/W

+CP3EN0*UINT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Communications

0200028

D15–5

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

block CP4

(HW)

D4

CP4EN4

Map UINT4 interrupt requests to CP4

1

Enable

0

 

Disable

0

R/W

CP4= CP4EN4*UINT4

interrupt select

 

D3

CP4EN3

Map UINT3 interrupt requests to CP4

1

Enable

0

 

Disable

0

R/W

+CP4EN3*UINT3

register

 

D2

CP4EN2

Map UINT2 interrupt requests to CP4

1

Enable

0

 

Disable

0

R/W

+CP4EN2*UINT2

 

 

D1

CP4EN1

Map UINT1 interrupt requests to CP4

1

Enable

0

 

Disable

0

R/W

+CP4EN1*UINT1

 

 

D0

CP4EN0

Map UINT0 interrupt requests to CP4

1

Enable

0

 

Disable

0

R/W

+CP4EN0*UINT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Communications

020002A

D15–12

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

block modem

(HW)

D11

RI

RI input status

 

 

1

RI="L"

0

 

RI="H"

X

R

 

status register

 

D10

CTS

CTS input status

 

 

1

CTS="L"

0

 

CTS="H

X

R

 

 

 

D9

DCD

DCD input status

 

 

1

DCD="L"

0

 

DCD="H"

X

R

 

 

 

D8

DSR

DSR input status

 

 

1

DSR="L"

0

 

DSR="H"

X

R

 

 

 

D7

SDRI

RI input status 1 →

0

 

1

Changed

0

 

No change

0

R/W

Write "1" to clear.

 

 

D6

SURI

RI input status 0 →

1

 

1

Changed

0

 

No change

0

R/W

Write "1" to clear.

 

 

D5

SDCTS

CTS input status 1 →

 

0

1

Changed

0

 

No change

0

R/W

Write "1" to clear.

 

 

D4

SUCTS

CTS input status 0 →

 

1

1

Changed

0

 

No change

0

R/W

Write "1" to clear.

 

 

D3

SDDCD

DCD input status 1 →

0

1

Changed

0

 

No change

0

R/W

Write "1" to clear.

 

 

D2

SUDCD

DCD input status 0 →

1

1

Changed

0

 

No change

0

R/W

Write "1" to clear.

 

 

D1

SDDSR

DSR input status 1 →

0

1

Changed

0

 

No change

0

R/W

Write "1" to clear.

 

 

D0

SUDSR

DSR input status 0 →

1

1

Changed

0

 

No change

0

R/W

Write "1" to clear.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Communications

020002C

D15–8

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

block modem

(HW)

D7

EDRI

Enable SDRI interrupts

1

Enable

0

 

Disable

0

R/W

 

status interrupt

 

D6

EURI

Enable SURI interrupts

1

Enable

0

 

Disable

0

R/W

 

enable register

 

D5

EDCTS

Enable SDCTS interrupts

1

Enable

0

 

Disable

0

R/W

 

 

 

D4

EUCTS

Enable SUCTS interrupts

1

Enable

0

 

Disable

0

R/W

 

 

 

D3

EDDCD

Enable SDDCD interrupts

1

Enable

0

 

Disable

0

R/W

 

 

 

D2

EUDCD

Enable SUDCD interrupts

1

Enable

0

 

Disable

0

R/W

 

 

 

D1

EDDSR

Enable SDDSR interrupts

1

Enable

0

 

Disable

0

R/W

 

 

 

D0

EUDSR

Enable SUDSR interrupts

1

Enable

0

 

Disable

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Communications

020002E

D15–2

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

block modem

(HW)

D1

DTR

DTR output level

 

 

1

DTR="H"

0

 

DTR="L"

0

R/W

Only valid for UART

control register

 

D0

RTS

RTS output level

 

 

1

RTS="H"

0

 

RTS="L"

0

R/W

operation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Communications

0200032

D15–1

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

block debugging

(HW)

D0

STOP

Debugging HOLD input control

1

HOLD input

0

 

No input

0

R/W

 

@ mode register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PDC interrupt

0200100

D15–2

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

register

(HW)

D1

INTE

PDC interrupt enable

 

1

Enable

0

 

Disable

0

R/W

 

 

 

D0

PDCINT

PDC interrupt flag

 

 

1

Request pending

0

 

No interrupts

X

R/W

Write "1" to clear

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PDC command

0200102

D15–3

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

register

(HW)

D2

TXBS

PDC transmit buffer select

1

Buffer B

0

 

Buffer A

0

R/W

 

 

 

D1

TXEN

PDC transmit enable

 

1

Enable

0

 

Disable

0

R/W

 

 

 

D0

RXEN

PDC receive enable

 

1

Enable

0

 

Disable

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PDC status

0200104

D15–8

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

register

(HW)

D7

CRCER1

PDC receive data CRC-16 error flag

1

CRC error

0

 

No error

X

R

 

 

 

D6

CRCER2

PDC receive data CRC-CCITT error flag

1

CRC error

0

 

No error

X

R

 

 

 

D5–2

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

 

 

D1

RXBB

Receive buffer B status

1

Input available

0

 

No input

X

R

 

 

 

D0

RXBA

Receive buffer A status

1

Input available

0

 

No input

X

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PHS transmit

0200200

D15–8

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

control register

(HW)

D7

TXINTE

PHS transmit interrupt enable

1

Enable

0

 

Disable

0

R/W

 

 

 

D6–2

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

 

 

D1

TXBS

PHS transmit buffer select

1

Buffer B

0

 

Buffer A

0

R/W

 

 

 

D0

TXEN

PHS transmit enable

 

1

Enable

0

 

Disable

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PHS transmit

0200202

D15–8

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

status register

(HW)

D7

TXINT

PHS transmit interrupt flag

1

Request pending

0

 

No interrupts

0

R/W

Write "1" to clear

 

 

D6–0

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PHS receive

0200204

D15–8

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

control register

(HW)

D7

RXINTE

PHS receive interrupt enable

1

Enable

0

 

Disable

0

R/W

 

 

 

D6–1

–

–

 

 

 

–

 

 

 

–

–

0 when being read.

 

 

D0

RXEN

PHS receive enable

 

1

Enable

0

 

Disable

0

R/W

 

B-III-10-22

EPSON

S1C33210 FUNCTION PART