III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
ABORT: HDLC Abort detected (D7) / HDLC E/S INT receive status register (0x020032C)
TXUE: HDLC Tx underrun/EOM detected (D5) / HDLC E/S INT receive status register (0x020032C)
Hunt: HDLC Hunt detected (D1) / HDLC E/S INT receive status register (0x020032C)
IDLED: HDLC Idle detected (D0) / HDLC E/S INT receive status register (0x020032C)
These bits give the status for E/S INT interrupt triggers.
A "1" in ABORT indicates the detection of seven or more "1" bits while receive operation is enabled. If Abort interrupts are disabled, however, this bit immediately returns to "0" after the next "0" bit. Otherwise, there is an E/S INT interrupt request, and the hardware latches this bit until the next reset E/S INT command. If there is no abort pattern in the input, this command resets this bit to "0," and there is another E/S INT interrupt request.
The ABORT bit behaves differently from other E/S INT status flags. The hardware remembers all transitions even when other sources latch the corresponding flags. If ABORT changes from "0" to "1" and back to "0" while an E/S INT interrupt request from another source is pending, for example, the next reset E/S INT command clears that interrupt request, but there is then another interrupt request for the ABORT transition from "0" to "1." The next reset E/S INT command clears that interrupt request, but there is yet another interrupt request for the ABORT transition back to "0." Note, however, that ABORT never goes to "1" if Abort interrupts are disabled.
After the hardware detects an abort pattern, it immediately shifts to flag detection. This pattern of equating an abort pattern with loss of flag synchronization and then shifting to flag detection applies whenever receive operation is enabled, regardless of the receive compare enable or other settings.
A "1" in TXUE indicates an empty transmit queue (underrun/EOM) during or after a frame. The transition from "0" to "1" forces transmission of a CRC or abort pattern as specified by the CRC/Abort on underrun/EOM bit in the HDLC transmit operation settings register (D1/0x0200318). If the bit is already "1," the hardware skips this step. The hardware then sends a closing flag pattern. Note that sending a CRC or abort pattern before the closing flag pattern requires resetting this bit to "0" with a reset Tx underrun/OEM latch command (D[7]/0x020031C).
This bit also goes to "1" after a disable transmit or send abort (D[6]/0x020031C) command. The reverse transition, from "1" to "0," produces an E/S INT interrupt.
This bit is the same as TXUE in the HDLC transmit status register (D7/0x0200334).
A "1" in Hunt indicates loss of flag synchronization. This bit is "0" when the hardware is idle waiting for a flag pattern, receiving a frame, etc. It goes to "1" after a disable receive command, enter hunt mode command, or detection of an abort pattern. In particular, note that bit transitions in either direction produce E/S INT interrupt requests.
A "1" in IDLED indicates an idle state, 15 or more "1" bits in a row. If idle detection is disabled, nothing more happens. Otherwise, the transition from "0" to "1" produces an E/S INT interrupt request and latches the bit until the next reset E/S INT command. If the idle state is still in effect, however, there is then another E/S INT interrupt request. Note that idle detection includes abort detection.
EPSON | S1C33210 FUNCTION PART |