6 BASIC EXTERNAL WIRING DIAGRAM
6 Basic External Wiring Diagram
External
Bus
HSDMA
Serial I/O
A/D input
Timer input/output
Input
I/O
Mobile access Interface input
Mobile access Interface output
A[23:0] |
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| VDD |
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D[15:0] |
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#RD |
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| AVDD |
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#DRD |
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| 3.3V | |||||||||
#GARD |
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| DSIO |
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#GAAS |
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#WRL/#WR/#WE |
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#WRH/#BSH |
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#DWR |
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#HCAS |
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#LCAS |
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| EA10MD0 |
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#CExx/#RASx |
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#CE10EX |
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| EA10MD1 |
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#WAIT |
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BCLK |
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#BUSREQ |
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| #X2SPD |
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#BUSACK |
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| ∗ 1 |
| C2 |
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#BUSGET |
| S1C33210 |
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| C1 |
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#NMI |
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| PLLC |
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| R1 |
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#DMAREQx | [The potential of the substrate |
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(back of the chip) is VSS.] | PLLS0 |
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#DMAACKx |
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#DMAENDx |
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| PLLS1 |
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SINx |
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SOUTx |
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| OSC3 |
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#SCLKx |
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| X'tal2 |
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| CG2 |
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#SRDYx |
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| Rf2 |
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#ADTRG |
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| OSC4 |
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| CR |
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| CD2 |
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ADx |
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EXCLx |
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| OSC1 |
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| CG1 |
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TMx |
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| X'tal1 |
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T8UFx |
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| OSC2 |
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Kxx |
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| #RESET |
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Pxx |
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RI |
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| VSS |
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CTS |
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DSR |
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RXD |
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MSEL |
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DTR |
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RTS |
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TXD |
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CNT1 |
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CNT2 |
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GOUT |
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X'tal1 | Crystal oscillator |
| 32.768 kHz, CI(Max.) = 34 kΩ | ∗ 1: When the PLL is not used, |
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CG1 | Gate capacitor |
| 10 pF |
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| leave the PLLC pin open. |
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CD1 | Drain capacitor |
| 10 pF |
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Rf1 | Feedback resistor | 10 MΩ |
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X'tal2 | Crystal oscillator |
| 33 MHz (Max.) |
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CR | Ceramic oscillator | 33 MHz (Max.) |
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CG2 | Gate capacitor |
| 10 pF |
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CD2 | Drain capacitor |
| 10 pF |
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Rf2 | Feedback resistor | 1 MΩ |
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R1 | Resistor |
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| 4.7 kΩ |
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C1 | Capacitor |
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| 100 pF |
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C2 | Capacitor |
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| 5 pF |
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Note: The above table is simply an example, and is not guaranteed to work.
S1C33210 PRODUCT PART | EPSON |