1 OUTLINE

Pin name

Pin No.

I/O

Pull-up

 

 

 

Function

 

QFP15-128

 

 

 

 

 

 

 

#CE4

35

O

–

#CE4:

Area 4 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00"

#CE11

 

 

 

 

 

(default)

 

 

#CE11&12

 

 

 

#CE11:

Area 11 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01"

 

 

 

 

* When CEFUNC[1:0] = "1x", this pin outputs #CE11+#CE12 signal.

#RD

24

O

–

Read signal

 

 

 

#WRL

20

O

–

#WRL:

Write (low byte) signalwhen SBUSST(D3/0x4812E) = "0" (default)

#WR

 

 

 

#WR:

Write signal when SBUSST(D3/0x4812E) = "1"

#WE

 

 

 

#WE:

DRAM write signal

#WRH

21

O

–

#WRH:

Write (high byte) signal when SBUSST(D3/0x4812E) = "0"

#BSH

 

 

 

 

 

(default)

 

 

 

 

 

 

#BSH:

Bus strobe (high byte) signal when SBUSST(D3/0x4812E) = "1"

#HCAS

60

O

–

#HCAS:

DRAM column address strobe (high byte) signal

#LCAS

61

O

–

#LCAS:

DRAM column address strobe (low byte) signal

BCLK

4

O

–

Bus clock output

 

 

P34

62

I/O

–

P34:

I/O port when CFP34(D4/0x402DC) = "0" (default)

#BUSREQ

 

 

 

#BUSREQ:

Bus release request input when CFP34(D4/0x402DC) = "1"

#CE6

 

 

 

#CE6:

Area 6 chip enable when CFP34(D4/0x402DC) = "1" and

 

 

 

 

 

 

IOC34(D4/0x402DE) = "1"

P35

59

I/O

–

P35:

I/O port when CFP35(D5/0x402DC) = "0" (default)

#BUSACK

 

 

 

#BUSACK:

Bus acknowledge output when CFP35(D5/0x402DC) = "1"

P30

68

I/O

–

P30:

I/O port when CFP30(D0/0x402DC) = "0" (default)

#WAIT

 

 

 

#WAIT:

Wait cycle request input when CFP30(D0/0x402DC) = "1"

#CE4&5

 

 

 

#CE4&5:

Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and

 

 

 

 

 

 

IOC30(D0/0x402DE) = "1"

P20

92

I/O

–

P20:

I/O port when CFP20(D0/0x402D8) = "0" (default)

#DRD

 

 

 

#DRD:

DRAM read signal output for successive RAS mode when

 

 

 

 

 

 

CFP20(D0/0x402D8) = "1"

P21

117

I/O

–

P21:

I/O port when CFP21(D1/0x402D8) = "0" and

#DWE

 

 

 

 

 

CFEX2(D2/0x402DF) = "0" (default)

#GAAS

 

 

 

#DWE:

DRAM read signal output for successive RAS mode when

 

 

 

 

 

 

CFP21(D1/0x402D8) = "1" and CFEX2(D2/0x402DF) = "0"

 

 

 

 

#GAAS:

Area address strobe for GA when CFEX2(D2/0x402DF) = "1"

P31

11

I/O

–

P31:

I/O port when CFP31(D1/0x402DC) = "0" and

#BUSGET

 

 

 

 

 

CFEX3(D3/0x402DF) = "0" (default)

#GARD

 

 

 

#BUSGET: Bus status monitorsignal output when CFP31(D1/0x402DC) = "1"

 

 

 

 

 

 

and CFEX3(D3/0x402DF) = "0"

 

 

 

 

#GARD:

Area read signal output for GA when CFEX3(D3/0x402DF) = "1"

EA10MD1

115

I

Pull-up

Area 10 boot mode selection

 

 

 

 

 

EA10MD1 EA10MD0

Mode

 

 

 

 

 

1

1

External ROM mode

EA10MD0

114

I

–

1

0

–

 

 

 

 

0

1

–

 

 

 

 

0

0

–

A-6

EPSON

S1C33210 PRODUCT PART