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| 1 OUTLINE |
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| Table 1.3.3 List of Pins for HSDMA Control Signals | ||||
Pin name | Pin No. |
| I/O |
| Function | |
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K50 | 19 |
| I | K50: | Input port when CFK50(D0/0x402C0) = "0" (default) | |
#DMAREQ0 |
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| #DMAREQ0: | HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1" |
K51 | 23 |
| I | K51: | Input port when CFK51(D1/0x402C0) = "0" (default) | |
#DMAREQ1 |
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| #DMAREQ1: | HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1" |
P32 | 13 |
| I/O | – | P32: | I/O port when CFP32(D2/0x402DC) = "0" (default) |
#DMAACK0 |
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| #DMAACK0: HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) | |
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| = "1" |
P33 | 15 |
| I/O | – | P33: | I/O port when CFP33(D3/0x402DC) = "0" (default) |
#DMAACK1 |
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| #DMAACK1: HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) | |
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| = "1" |
P04 | 83 |
| I/O | – | P04: | I/O port when CFP04(D4/0x402D0) = "0" and |
SIN1 |
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| CFEX4(D4/0x402DF) = "0" (default) |
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| SIN1: | Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1" and |
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| CFEX4(D4/0x402DF) = "0" |
P15 | 128 |
| I/O | – | P15: | I/O port when CFP15(D5/0x402D4) = "0" (default) |
EXCL4 |
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| EXCL4: | |
#DMAEND0 |
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| "1" and IOC15(D5/0x402D6) = "0" |
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| #DMAEND0: HSDMA Ch. 0 | |
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| CFP15(D5/0x402D4) = "1" and IOC15(D5/0x402D6) = "1" |
P16 | 77 |
| I/O | – | P16: | I/O port when CFP16(D6/0x402D4) = "0" (default) |
EXCL5 |
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| EXCL5: | |
#DMAEND1 |
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| "1" and IOC16(D6/0x402D6) = "0" |
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| #DMAEND1: HSDMA Ch. 1 | |
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| CFP16(D6/0x402D4) = "1" and IOC16(D6/0x402D6) = "1" |
P05 | 86 |
| I/O | – | P05: | I/O port when CFP05(D5/0x402D0) = "0" and |
SOUT1 |
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| CFEX5(D5/0x402DF) = "0" (default) |
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| SOUT1: | Serial I/F Ch. 1 data outputwhen CFP05(D5/0x402D0)= "1" and |
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| CFEX5(D5/0x402DF) = "0" |
S1C33210 PRODUCT PART | EPSON |