II CORE BLOCK: BCU (Bus Control Unit)

CRAS: Successive RAS mode (D8) / DRAM timing set-up register (0x48130)

Set the successive RAS mode.

Write "1": Successive RAS mode

Write "0": Normal mode

Read: Valid

In systems using DRAM, the successive RAS mode is entered by writing "1" to CRAS. In this mode, read/write operations can be performed in page mode even when DRAM accesses do not occur back-to-back.

When using the successive RAS mode, be sure to use #DRD for the read signal and #DWE for the write signal for low-byte.

When CRAS = "0", random read/write cycles are used for non-successive DRAM accesses. The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.

At cold start, CRAS is set to "0" (normal mode). At hot start, CRAS retains its status before being initialized.

RPRC1–RPRC0: Number of RAS precharge cycles (D[7:6]) / DRAM timing set-up register (0x48130)

Select the number of precharge cycles during a DRAM access.

Table 4.26 Number of RAS Precharge Cycles

RPRC1

RPRC0

Number of cycles

1

1

4 cycles

1

0

3 cycles

0

1

2 cycles

0

0

1 cycle

The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.

At cold start, RPRC is set to "0" (1 cycle). At hot start, RPRC retains its status before being initialized.

CASC1–CASC0: Number of CAS cycles (D[4:3]) / DRAM timing set-up register (0x48130)

Select the number of CAS cycles during a DRAM access.

Table 4.27 Number of CAS Cycles

CASC1

CASC0

Number of cycles

1

1

4 cycles

1

0

3 cycles

0

1

2 cycles

0

0

1 cycle

The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.

At cold start, CASC is set to "0" (1 cycle). At hot start, CASC retains its status before being initialized.

RASC1–RASC0: Number of RAS cycles (D[1:0]) / DRAM timing set-up register (0x48130)

Select the number of RAS cycles during a DRAM access.

Table 4.28 Number of RAS Cycles

RASC1

RASC0

Number of cycles

1

1

4 cycles

1

0

3 cycles

0

1

2 cycles

0

0

1 cycle

The contents set here are applied to all of areas 14, 13, 8, and 7 that are set for DRAM.

At cold start, RASC is set to "0" (1 cycle). At hot start, RASC retains its status before being initialized.

S1C33210 FUNCTION PART

EPSON

B-II-4-43