II CORE BLOCK: CLG (Clock Generator)

I/O Memory of Clock Generator

Table 6.4 lists the control bits of clock generator.

Table 6.4 Control Bits of Clock Generator

Register name

Address

Bit

Name

Function

 

 

 

 

 

Setting

 

Init.

R/W

Remarks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Power control

0040180

D7

CLKDT1

System clock division ratio

CLKDT[1:0]

 

Division ratio

0

R/W

 

register

(B)

D6

CLKDT0

selection

 

1

 

1

 

 

 

 

1/8

0

 

 

 

 

 

 

 

 

1

 

0

 

 

 

 

1/4

 

 

 

 

 

 

 

 

 

0

 

1

 

 

 

 

1/2

 

 

 

 

 

 

 

 

 

0

 

0

 

 

 

 

1/1

 

 

 

 

 

D5

PSCON

Prescaler On/Off control

1

 

On

 

 

 

0

 

Off

1

R/W

 

 

 

D4–3

–

reserved

 

 

 

 

 

 

–

 

0

–

Writing 1 not allowed.

 

 

D2

CLKCHG

CPU operating clock switch

1

 

OSC3

 

 

0

 

OSC1

1

R/W

 

 

 

D1

SOSC3

High-speed (OSC3) oscillation On/Off

1

 

On

 

 

 

0

 

Off

1

R/W

 

 

 

D0

SOSC1

Low-speed (OSC1) oscillation On/Off

1

 

On

 

 

 

0

 

Off

1

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock option

0040190

D7–4

–

–

 

 

 

 

 

 

–

 

–

–

0 when being read.

register

(B)

D3

HLT2OP

HALT clock option

1

 

On

 

 

 

0

 

Off

0

R/W

 

 

 

D2

8T1ON

OSC3-stabilize waiting function

1

 

Off

 

 

 

0

 

On

1

R/W

 

 

 

D1

–

reserved

 

 

 

 

 

 

–

 

0

–

Do not write 1.

 

 

D0

PF1ON

OSC1 external output control

1

 

On

 

 

 

0

 

Off

0

R/W

 

 

 

 

 

 

 

 

 

 

Power control

004019E

D7

CLGP7

Power control register protect flag

Writing 10010110 (0x96)

0

R/W

 

protect register

(B)

D6

CLGP6

 

removes the write protection of

0

 

 

 

 

D5

CLGP5

 

the power control register

0

 

 

 

 

D4

CLGP4

 

(0x40180) and the clock option

0

 

 

 

 

D3

CLGP3

 

register (0x40190).

 

0

 

 

 

 

D2

CLGP2

 

Writing another value set the

0

 

 

 

 

D1

CLGP1

 

write protection.

 

0

 

 

 

 

D0

CLGP0

 

 

 

 

 

 

 

 

 

 

 

0

 

 

SOSC1: Low-speed (OSC1) oscillation control (D0) / Power control register (0x40180)

Turns the low-speed (OSC1) oscillation on or off.

Write "1": OSC1 oscillation turned on

Write "0": OSC1 oscillation turned off

Read: Valid

The oscillation of the low-speed (OSC1) oscillation circuit is stopped by writing "0" to SOSC1, and started again by writing "1".

Since a duration of maximum three seconds is required for oscillation to stabilize after the oscillation has been restarted, at least this length of time must pass before the OSC1 clock can be used.

Writing to SOSC1 is allowed only when CLGP[7:0] is set to "0b10010110". Note also that if the CPU is operating using the OSC1 clock, writing "0" to SOSC1 is ignored and the oscillation is not turned off.

At initial reset, SOSC1 is set to "1" (OSC1 oscillation turned on).

Note: This control bit is effective only when the low-speed (OSC1) oscillation circuit in the Peripheral Block is used.

SOSC3: High-speed (OSC3) oscillation control (D1) / Power control register (0x40180)

Turns the high-speed (OSC3) oscillation on or off.

Write "1": OSC3 oscillation turned on

Write "0": OSC3 oscillation turned off

Read: Valid

The oscillation of the high-speed (OSC3) oscillation circuit is stopped by writing "0" to SOSC3, and started again by writing "1".

Since a duration of maximum 10 ms (for a 3.3-V crystal resonator) is required for oscillation to stabilize after the oscillation has been restarted, at least this length of time must pass before the OSC3 clock can be used.

Writing to SOSC3 is allowed only when CLGP[7:0] is set to "0b10010110". Note also that if the CPU is operating using the OSC3 clock, writing "0" to SOSC3 is ignored and the oscillation is not turned off.

At initial reset, SOSC3 is set to "1" (OSC3 oscillation turned on).

B-II-6-6

EPSON

S1C33210 FUNCTION PART