II CORE BLOCK: BCU (Bus Control Unit)

External Memory Map and Chip Enable

The BCU has a 24-bit external address bus (A[23:0]) and a 16-bit external data bus (D[15:0]), allowing an address space of up to 16 MB to be accessed with one chip enable signal. By default, the address space is divided into 11 areas (areas 0 to 10) for management purposes. Of these, areas 4 to 10 are open to an external system, each provided with an independent chip-enable pin (#CE[10:4]).

The C33 Core Block is limited to 24 available pins for the address bus and 7 pins for the #CE output due to its package structure. However, the #CE[4:10] output pins can be switched to the high-order area chip enable output pins as shown in Table 4.5 using software. CEFUNC[1:0] (D[A:9]) / DRAM timing set-up register (0x48130) is used for this switching.

Table 4.5 Switching of #CE Output

Pin

CEFUNC = "00"

CEFUNC = "01"

CEFUNC = "1x"

#CE4

#CE4

#CE11

#CE11+#CE12

#CE5

#CE5

#CE15

#CE15+#CE16

#CE6

#CE6

#CE6

#CE7+#CE8

#CE7/#RAS0

#CE7/#RAS0

#CE13/#RAS2

#CE13/#RAS2

#CE8/#RAS1

#CE8/#RAS1

#CE14/#RAS3

#CE14/#RAS3

#CE9

#CE9

#CE17

#CE17+#CE18

#CE10EX

#CE10EX

#CE10EX

#CE9+#CE10EX

(Default: CEFUNC = "00")

The high-order areas that are made available for use by writing "01" to CEFUNC can be larger in size than the default low-order areas. For example, when using DRAM in default settings, the available space is 4 MB in areas 7 and 8. However, if areas 13 and 14 are used, up to 32 MB of DRAM can be used. The same applies to the other areas. Furthermore, when CEFUNC is set to "10" or "11", five chip enable signals are expanded into two area size. Although the C33 Core Block has only 24 address output pins, it features 28-bit internal address processing.

Figure 4.2 shows a memory map for an external system.

Area

Address

 

Area 10 (#CE10)

0x0FFFFFF

 

SRAM type

 

External memory 6 (4MB)

Burst ROM type

 

 

 

8 or 16 bits

0x0C00000

 

Area 9 (#CE9)

0x0BFFFFF

 

SRAM type

 

External memory 5 (4MB)

Burst ROM type

 

 

 

8 or 16 bits

0x0800000

 

Area 8 (#CE8/#RAS1)

0x07FFFFF

 

SRAM type

 

External memory 4 (2MB)

DRAM type

 

 

 

8 or 16 bits

0x0600000

 

Area 7 (#CE7/#RAS0)

0x05FFFFF

 

SRAM type

 

External memory 3 (2MB)

DRAM type

 

 

 

8 or 16 bits

0x0400000

 

Area 6 (#CE6)

0x03FFFFF

External I/O (16-bit device)

SRAM type

0x0380000

 

 

0x037FFFF

External I/O (8-bit device)

 

0x0300000

 

 

Area 5 (#CE5)

0x02FFFFF

 

SRAM type

 

Internal I/O memory

 

 

 

0x0200000

 

Area 4 (#CE4)

0x01FFFFF

 

SRAM type

 

External memory 1 (1MB)

8 or 16 bits

 

 

 

 

0x0100000

 

 

CEFUNC = "00"

Area

Address

 

 

Area 17 (#CE17)

0xBFFFFFF

(Mirror of External memory 6)

 

SRAM type

 

0x9000000

 

 

8 or 16 bits

0x8FFFFFF

External memory 6 (16MB)

 

 

0x8000000

 

 

 

 

Area 15 (#CE15)

0x5FFFFFF

(Mirror of External memory 5)

 

SRAM type

 

0x5000000

 

 

8 or 16 bits

0x4FFFFFF

External memory 5 (16MB)

 

 

0x4000000

 

 

 

 

Area 14 (#CE14/#RAS3)

0x3FFFFFF

 

 

SRAM type

 

External memory 4 (16MB)

 

DRAM type

 

 

 

 

 

8 or 16 bits

0x3000000

 

 

Area 13 (#CE13/#RAS2)

0x2FFFFFF

 

 

SRAM type

 

External memory 3 (16MB)

 

DRAM type

 

 

 

 

 

8 or 16 bits

0x2000000

 

 

Area 11 (#CE11)

0x17FFFFF

 

 

SRAM type

 

External memory 2 (8MB)

 

8 or 16 bits

 

 

 

 

 

 

0x1000000

 

 

Area 10 (#CE10)

0x0FFFFFF

 

 

SRAM type

 

External memory 1 (4MB)

 

Burst ROM type

 

 

 

 

 

8 or 16 bits

0x0C00000

 

 

Area 6 (#CE6)

0x03FFFFF

External I/O (16-bit device)

 

SRAM type

0x0380000

 

 

 

 

0x037FFFF

External I/O (8-bit device)

 

 

0x0300000

 

 

 

 

 

CEFUNC = "01"

S1C33210 FUNCTION PART

EPSON

B-II-4-5