1 OUTLINE
1.2 Block Diagram
VDD 
VSS 
A[23:0]
D[15:0]
#RD 
#WRL/#WR/#WE 
#WRH/#BSH 
#HCAS 
#LCAS 
#CE10EX #CE[9:4] 
#WAIT(P30) 
#DRD(P20) 
#DWE(P21) 
#GAAS(P21) 
#GARD(P31) 
S1C33000
CPU Core
Bus Control Unit
#RESET
#NMI
#X2SPD
TST
DSIO
EA10MD[1:0]
BCLK
#BUSREQ(P34)
#BUSACK(P35)
#BUSGET(P31)
DPCO(P13) 
DCLK(P14)
OSC3 |
|
|
|
|
|
|
|
OSC4 |
|
|
|
|
| OSC3/PLL | |
|
|
|
| ||||
PLLS[1:0] |
|
|
|
|
| ||
|
|
|
|
| |||
|
|
|
|
| |||
|
|
|
|
|
|
| |
PLLC |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
|
|
|
|
|
|
| |
|
|
|
|
|
| ||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
|
|
|
|
|
| Prescaler | |
OSC1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
OSC2 |
|
|
|
|
| OSC1 | |
|
|
|
| ||||
FOSC1(P14) |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
|
|
|
|
|
| ||
|
|
|
|
|
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| Clock | |
|
|
|
|
|
| Timer | |
|
|
|
|
|
|
| |
|
|
|
|
|
|
| |
|
|
|
|
|
| Intelligent | |
|
|
|
|
|
| DMA (128 ch.) | |
#DMAREQx(K50, K51) |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
#DMAACKx(P32, P33) |
|
|
|
|
| ||
|
|
|
|
| |||
|
|
|
|
| DMA (4 ch.) | ||
#DMAENDx(P15, P16) |
|
|
|
|
| ||
|
|
|
|
| |||
|
|
|
|
|
|
| |
|
|
|
|
|
|
| |
|
|
|
|
|
|
| |
|
|
|
|
|
| RAM | |
|
|
|
|
|
| 8KB | |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Interrupt
Controller
Programmable
Timer (6 ch.)
Programmable
Timer (6 ch.)
Serial Interface
(4 ch.)
A/D Converter
(4 ch.)
Input Port
I/O Port
Mobile Access
Interface
SINx(P00, P04, P27, RXD)
SOUTx(P01, P05, P26, TXD)
#SCLKx(P02, P25)
#SRDYx(P03, P24)
#ADTRG(K52)
AVDD
DTR
RTS
TXD
RI
CTS
DCD
DSR
RXD
CNT1
CNT2
MSEL
GOUT
Figure 1.2.1 S1C33210 Block Diagram
S1C33210 PRODUCT PART | EPSON |