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| 4 | PERIPHERAL CIRCUITS | ||
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Register name | Address | Bit | Name | Function |
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| Setting |
| Init. | R/W | Remarks | ||||
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Communications | 0200000 | – | – |
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| – |
| – | – | 0 when being read. | |||
macro select | (HW) | D1 | MCRS1 | Master configuration selection | MCRS[1:0] |
| Communications mode | 0 | R/W | Only valid when | |||||||
register |
| D0 | MCRS0 |
| 1 |
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| 1 |
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| PHS | 0 |
| MSEL pin input is at | |
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| 1 |
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| 0 |
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| PDC |
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| High level | |
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| 0 |
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| 1 |
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| HDLC |
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| 0 |
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| 0 |
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| UART |
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Software reset | 0200002 | – | – |
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| – |
| – | – | 0 when being read. | |||
register | (HW) | D2 | PHSRST | Reset PHS communications block | 1 | Reset |
| 0 | Ignored | 0 | W |
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| D1 | PDCRST | Reset PDC communications block | 1 | Reset |
| 0 | Ignored | 0 | W |
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| D0 | HDLRST | Reset HDLC communications block | 1 | Reset |
| 0 | Ignored | 0 | W |
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Communications | 0200004 | – | – |
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| – |
| – | – | 0 when being read. | |||
block clock | (HW) | D3 | CKD3 | Specify clock frequency divider |
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| CKD[3:0] |
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| Net frequency | 1 | R/W | fout = PERICLK | ||||
frequency |
| D2 | CKD2 | for communications block | 1 |
| 1 | 1 |
| 1 |
| fout/16 | 1 | R/W | output | ||
divider register |
| D1 | CKD1 |
| 1 |
| 1 | 1 |
| 0 |
| fout/15 | 1 | R/W | frequency | ||
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| D0 | CKD0 |
| 1 |
| 1 | 0 |
| 1 |
| fout/14 | 1 | R/W |
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| 1 |
| 1 | 0 |
| 0 |
| fout/13 |
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| 1 |
| 0 | 1 |
| 1 |
| fout/12 |
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| 1 |
| 0 | 1 |
| 0 |
| fout/11 |
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| 1 |
| 0 | 0 |
| 1 |
| fout/10 |
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| 1 |
| 0 | 0 |
| 0 |
| fout/9 |
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| 0 |
| 1 | 1 |
| 1 |
| fout/8 |
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| 0 |
| 1 | 1 |
| 0 |
| fout/7 |
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| 0 |
| 1 | 0 |
| 1 |
| fout/6 |
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| 0 |
| 1 | 0 |
| 0 |
| fout/5 |
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| 0 |
| 0 | 1 |
| 1 |
| fout/4 |
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| 0 |
| 0 | 1 |
| 0 |
| fout/3 |
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| 0 |
| 0 | 0 |
| 1 |
| fout/2 |
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| 0 |
| 0 | 0 |
| 0 |
| fout/2 |
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Communications | 020000A | – | – |
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| – |
| – | – | 0 when being read. | |||
block output port | (HW) | D3 | MOPORT3 | RTS output level | 1 | RTS="L" |
| 0 | RTS="H" | 1 | R/W | Only valid for PHS, PDC, | |||||
data register |
| D2 | MOPORT2 | DTR output level | 1 | DTR="L" |
| 0 | DTR="H" | 1 | R/W | and HDLC operation | |||||
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| D1 | CNT2 | CNT2 output level | 1 | CNT2="L" |
| 0 | CNT2="H" | 1 | R/W | Always valid | |||||
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| D0 | CNT1 | CNT1 output level | 1 | CNT1="L" |
| 0 | CNT1="H" | 1 | R/W |
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Communications | 020000C | – | – |
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| – |
| – | – | 0 when being read. | |||
block input port | (HW) | D7 | GOUTE | Enable GOUT output | 1 | Enable |
| 0 | Disable | 0 | R/W |
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data register |
| – | – |
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| – |
| – | – | 0 when being read. | |||
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| D1 | MIPORT1 | DSR input level | 1 | DSR="H" |
| 0 | DSR="L" | X | R |
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| D0 | MIPORT0 | RI input level | 1 | RI="H" |
| 0 | RI="L" | X | R |
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Communications | 0200010 | – | – |
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| – |
| – | – | 0 when being read. | |||
block PHS mode | (HW) | D2 | BMODE | Data conversion switch | 1 | Convert |
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| 0 | Pass through | 0 | R/W |
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settings register |
| D1 | BHALF | Speed switch for data conversion | 1 | 32kbps |
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| 0 | 64kbps | 0 | R/W |
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| D0 | FMODE | Frame frequency division switch | 1 | Frequency divider |
| 0 | Pass through | 0 | R/W |
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Communications | 0200020 | – | – |
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| – |
| – | – | 0 when being read. | |||
block CP0 | (HW) | D4 | CP0EN4 | Assign UINT4 to CP0 | 1 | Enable |
| 0 | Disable | 0 | R/W | CP0= CP0EN4*UINT4 | |||||
interrupt select |
| D3 | CP0EN3 | Assign UINT3 to CP0 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP0EN3*UINT3 | |||||
register |
| D2 | CP0EN2 | Assign UINT2 to CP0 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP0EN2*UINT2 | |||||
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| D1 | CP0EN1 | Assign UINT1 to CP0 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP0EN1*UINT1 | |||||
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| D0 | CP0EN0 | Assign UINT0 to CP0 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP0EN0*UINT0 | |||||
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Communications | 0200022 | – | – |
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| – |
| – | – | 0 when being read. | |||
block CP1 | (HW) | D4 | CP1EN4 | Assign UINT4 to CP1 | 1 | Enable |
| 0 | Disable | 0 | R/W | CP1= CP1EN4*UINT4 | |||||
interrupt select |
| D3 | CP1EN3 | Assign UINT3 to CP1 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP1EN3*UINT3 | |||||
register |
| D2 | CP1EN2 | Assign UINT2 to CP1 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP1EN2*UINT2 | |||||
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| D1 | CP1EN1 | Assign UINT1 to CP1 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP1EN1*UINT1 | |||||
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| D0 | CP1EN0 | Assign UINT0 to CP1 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP1EN0*UINT0 | |||||
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Communications | 0200024 | – | – |
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| – |
| – | – | 0 when being read. | |||
block CP2 | (HW) | D4 | CP2EN4 | Assign UINT4 to CP2 | 1 | Enable |
| 0 | Disable | 0 | R/W | CP2= CP2EN4*UINT4 | |||||
interrupt select |
| D3 | CP2EN3 | Assign UINT3 to CP2 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP2EN3*UINT3 | |||||
register |
| D2 | CP2EN2 | Assign UINT2 to CP2 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP2EN2*UINT2 | |||||
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| D1 | CP2EN1 | Assign UINT1 to CP2 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP2EN1*UINT1 | |||||
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| D0 | CP2EN0 | Assign UINT0 to CP2 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP2EN0*UINT0 | |||||
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Communications | 0200026 | – | – |
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| – |
| – | – | 0 when being read. | |||
block CP3 | (HW) | D4 | CP3EN4 | Assign UINT4 to CP3 | 1 | Enable |
| 0 | Disable | 0 | R/W | CP3= CP3EN4*UINT4 | |||||
interrupt select |
| D3 | CP3EN3 | Assign UINT3 to CP3 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP3EN3*UINT3 | |||||
register |
| D2 | CP3EN2 | Assign UINT2 to CP3 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP3EN2*UINT2 | |||||
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| D1 | CP3EN1 | Assign UINT1 to CP3 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP3EN1*UINT1 | |||||
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| D0 | CP3EN0 | Assign UINT0 to CP3 | 1 | Enable |
| 0 | Disable | 0 | R/W | +CP3EN0*UINT0 |
S1C33210 PRODUCT PART | EPSON |