III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
Data Buffers
PHS communications uses two
The transmit buffers are write only; the receive buffers, read only.
bit 15 ¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥
0x02007A0
0x020079F
Receive Buffer B (80 bytes)
0x0200750
0x020074F
Receive Buffer A (80 bytes)
0x0200700
0x02006FF
0x02006A0
0x020069F
Transmit Buffer B (80 bytes)
0x0200650
0x020064F
Transmit Buffer A (80 bytes)
0x0200600
Figure 10.11 PHS Communications Mode Data Buffers
FCS (CRC) Checking
PHS communications uses the following CRC polynomial for validating frame data integrity.
Figure 10.12 shows the range of application.
Serial data |
| Serial data (608 bits) |
|
Input for
Frame data (640 bits)
Figure 10.12 PHS Communications Mode FCS (CRC) Position
Output Port Control
For communications macro select(MCRS) register(D[1:0]/0x200000) setings other than
Input Port Monitoring
The MIPORT[1:0] bits in the communications block input port data register (D[1:0]/0x020000C) track the input levels for the DSR and RI pins. Note that the block does not store these values internally.
In this mode as in others, setting the GOUTE bit in the communications block input port data register (D7/0x020000C) to "1" connects the RI input to the GOUT output pin.
Note: Bits in the communications block modem status register (0x020002A) also track the input levels for the DSR and RI pins as well as transitions for triggering interrupt requests with changes in pin states.
EPSON | S1C33210 FUNCTION PART |