Epson S1C33210 manual 185

II CORE BLOCK: BCU (Bus Control Unit)

I/O Memory of BCU

Table 4.21 shows the control bits of the BCU. These I/O memories are mapped into the area (0x48000 and following addresses) used for the internal 16-bit peripheral circuits. However, these I/O memories can be accessed in bytes or words, as well as in half-words.

For the control bits of the external system interface pins assigned to the I/O ports, and for details on how to control the 8-bit programmable timer 0 in order to generate a DRAM refresh cycle, refer to each corresponding section in this manual.

Table 4.21 Control Bits of External System Interface

Register name	Address	Bit	Name	Function				Setting				Init.	R/W	Remarks
Areas 18–15	0048120	DF	–	reserved					–			–	–	0 when being read.
set-up register	(HW)	DE	A18SZ	Areas 18–17 device size selection	1	8 bits				0	16 bits	0	R/W
		DD	A18DF1	Areas 18–17	A18DF[1:0]				Number of cycles			1	R/W
		DC	A18DF0	output disable delay time	1			1			3.5	1
					1			0			2.5
					0			1			1.5
					0			0			0.5
		DB	–	reserved					–			–	–	0 when being read.
		DA	A18WT2	Areas 18–17 wait control	A18WT[2:0]					Wait cycles		1	R/W
		D9	A18WT1		1		1	1			7	1
		D8	A18WT0		1		1	0			6	1
					1		0	1			5
					1		0	0			4
					0		1	1			3
					0		1	0			2
					0		0	1			1
					0		0	0			0
		D7	–	reserved					–			–	–	0 when being read.
		D6	A16SZ	Areas 16–15 device size selection	1	8 bits				0	16 bits	0	R/W
		D5	A16DF1	Areas 16–15	A16DF[1:0]				Number of cycles			1	R/W
		D4	A16DF0	output disable delay time	1			1			3.5	1
					1			0			2.5
					0			1			1.5
					0			0			0.5
		D3	–	reserved					–			–	–	0 when being read.
		D2	A16WT2	Areas 16–15 wait control	A16WT[2:0]					Wait cycles		1	R/W
		D1	A16WT1		1		1	1			7	1
		D0	A16WT0		1		1	0			6	1
					1		0	1			5
					1		0	0			4
					0		1	1			3
					0		1	0			2
					0		0	1			1
					0		0	0			0
Areas 14–13	0048122	DF–9	–	reserved					–			–	–	0 when being read.
set-up register	(HW)	D8	A14DRA	Area 14 DRAM selection	1	Used				0	Not used	0	R/W
		D7	A13DRA	Area 13 DRAM selection	1	Used				0	Not used	0	R/W
		D6	A14SZ	Areas 14–13 device size selection	1	8 bits				0	16 bits	0	R/W
		D5	A14DF1	Areas 14–13	A14DF[1:0]				Number of cycles			1	R/W
		D4	A14DF0	output disable delay time	1			1			3.5	1
					1			0			2.5
					0			1			1.5
					0			0			0.5
		D3	–	reserved					–			–	–	0 when being read.
		D2	A14WT2	Areas 14–13 wait control	A14WT[2:0]					Wait cycles		1	R/W
		D1	A14WT1		1		1	1			7	1
		D0	A14WT0		1		1	0			6	1
					1		0	1			5
					1		0	0			4
					0		1	1			3
					0		1	0			2
					0		0	1			1
					0		0	0			0

S1C33210 FUNCTION PART EPSON B-II-4-33