1 OUTLINE
1.3.2 Pin Functions
Table 1.3.1 List of Pins for Power Supply System
Pin name | Pin No. | I/O | Function | |
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VDD | 8, 27, 47, 74, 93, 111 | – | – | Power supply (+) |
VSS | 3, 22, 39, 54, 67, 90, | – | (104 | Power supply |
| 102, 104 |
| Pull- |
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|
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| down) |
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AVDD | 30 | – | – | Analog system power supply (+); AVDD = VDD |
Table 1.3.2 List of Pins for External Bus Interface Signals
Pin name | Pin No. | I/O |
| Function | |
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A0 | 55 | O | – | A0: | Address bus (A0) when SBUSST(D3/0x4812E) = "0" (default) |
#BSL |
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| #BSL: | Bus strobe (low byte) signal when SBUSST(D3/0x4812E) = "1" |
A[23:1] | O | – | Address bus (A1 to A23) | ||
| 75, 78, 81, 84, 85, |
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| 91, 73, 76, 79, 82 |
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D[15:0] | 7, 10, 12, 14, 16, 18, 25,26, | I/O | – | Data bus (D0 to D15) | |
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#CE10EX | 34 | O | – | Area 10 chip enable for external memory | |
#CE9&10EX |
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| * When CEFUNC[1:0] = "1x", this pin outputs #CE9+#CE10EX signal. | |
#CE9 | 48 | O | – | #CE9: | Area 9 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00" |
#CE17 |
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| (default) |
#CE17&18 |
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| #CE17: | Area 17 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01" |
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| * When CEFUNC[1:0] = "1x", this pin outputs #CE17+#CE18 signal. | |
#CE8 | 53 | O | – | #CE8: | Area 8 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00" |
#RAS1 |
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| and A8DRA(D8/0x48128) = "0" (default) |
#CE14 |
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| #RAS1: | Area 8 DRAM row strobewhen CEFUNC[1:0](D[A:9])/0x48130) = |
#RAS3 |
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| "00" and A8DRA(D8/0x48128) = "1" |
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| #CE14: | Area 14 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01" |
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| or "1x" and A14DRA(D8/0x48122) = "0" |
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| #RAS3: | Area 14 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130) |
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| = "01"or "1x" and A14DRA(D8/0x48122) = "1" |
#CE7 | 49 | O | – | #CE7: | Area 7 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00" |
#RAS0 |
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| and A7DRA(D7/0x48128) = "0" (default) |
#CE13 |
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| #RAS0: | Area 7 DRAM row strobewhen CEFUNC[1:0](D[A:9])/0x48130) = |
#RAS2 |
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| "00" and A7DRA(D7/0x48128) = "1" |
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| #CE13: | Area 13 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01" |
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| or "1x" and A13DRA(D7/0x48122) = "0" |
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| #RAS2: | Area 13 DRAM row strobe when CEFUNC[1:0](D[A:9])/0x48130) |
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| = "01" or "1x" and A13DRA(D7/0x48122) = "1" |
#CE6 | 52 | O | – | Area 6 chip enable | |
#CE7&8 |
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| * When CEFUNC[1:0] = "1x", this pin outputs #CE7+#CE8 signal. | |
#CE5 | 71 | O | – | #CE5: | Area 5 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "00" |
#CE15 |
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|
| (default) |
#CE15&16 |
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| #CE15: | Area 15 chip enable when CEFUNC[1:0](D[A:9])/0x48130) = "01" |
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| * When CEFUNC[1:0] = "1x", this pin outputs #CE15+#CE16 signal. | |
S1C33210 PRODUCT PART | EPSON |