III PERIPHERAL BLOCK: PRESCALER
Register name | Address | Bit | Name | Function |
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| Setting | Init. | R/W | Remarks | |||
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004014E | D7 | P8TON3 |
| 1 | On |
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| 0 | Off | 0 | R/W |
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clock control | (B) | D6 | P8TS32 |
| P8TS3[2:0] |
| Division ratio | 0 | R/W | θ : selected by | ||||||
register |
| D5 | P8TS31 | clock division ratio selection |
| 1 |
| 1 | 1 |
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| θ /256 | 0 |
| Prescaler clock select | |
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| D4 | P8TS30 |
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| 1 |
| 1 | 0 |
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| θ /128 | 0 |
| register (0x40181) | |
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| 1 |
| 0 | 1 |
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| θ /64 |
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| 1 |
| 0 | 0 |
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| θ /32 |
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| 0 |
| 1 | 1 |
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| θ /16 |
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| generate the clock for | |
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| 0 |
| 1 | 0 |
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| θ /8 |
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| the serial I/F Ch.1. | |
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| 0 |
| 0 | 1 |
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| θ /4 |
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| 0 |
| 0 | 0 |
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| θ /2 |
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| D3 | P8TON2 |
| 1 | On |
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| 0 | Off | 0 | R/W |
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| D2 | P8TS22 |
| P8TS2[2:0] |
| Division ratio | 0 | R/W | θ : selected by | ||||||
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| D1 | P8TS21 | clock division ratio selection |
| 1 |
| 1 | 1 |
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| θ /4096 | 0 |
| Prescaler clock select | |
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| D0 | P8TS20 |
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| 1 |
| 1 | 0 |
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| θ /2048 | 0 |
| register (0x40181) | |
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| 1 |
| 0 | 1 |
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| θ /64 |
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| 1 |
| 0 | 0 |
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| θ /32 |
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| 0 |
| 1 | 1 |
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| θ /16 |
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| generate the clock for | |
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| 0 |
| 1 | 0 |
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| θ /8 |
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| the serial I/F Ch.0. | |
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| 0 |
| 0 | 1 |
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| θ /4 |
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| 0 |
| 0 | 0 |
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| θ /2 |
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A/D clock | 004014F | – | reserved |
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| – |
| – | – | 0 when being read. | ||
control register | (B) | D3 | PSONAD | A/D converter clock control | 1 | On |
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| 0 | Off | 0 | R/W |
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| D2 | PSAD2 | A/D converter clock division ratio |
| P8TS0[2:0] |
| Division ratio | 0 | R/W | θ : selected by | |||||
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| D1 | PSAD1 | selection | 1 |
| 1 | 1 |
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| θ /256 | 0 |
| Prescaler clock select | ||
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| D0 | PSAD0 |
| 1 |
| 1 | 0 |
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| θ /128 | 0 |
| register (0x40181) | ||
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| 1 |
| 0 | 1 |
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| θ /64 |
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| 1 |
| 0 | 0 |
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| θ /32 |
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| 0 |
| 1 | 1 |
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| θ /16 |
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| 0 |
| 1 | 0 |
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| θ /8 |
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| 0 |
| 0 | 1 |
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| θ /4 |
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| 0 |
| 0 | 0 |
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| θ /2 |
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Power control | 0040180 | D7 | CLKDT1 | System clock division ratio |
| CLKDT[1:0] |
| Division ratio | 0 | R/W |
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register | (B) | D6 | CLKDT0 | selection | 1 |
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| 1 |
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| 1/8 | 0 |
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| 1 |
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| 0 |
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| 1/4 |
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| 0 |
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| 1 |
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| 1/2 |
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| 0 |
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| 0 |
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| 1/1 |
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| D5 | PSCON | Prescaler On/Off control | 1 | On |
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| 0 | Off | 1 | R/W |
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| – | reserved |
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| – |
| 0 | – | Writing 1 not allowed. | ||
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| D2 | CLKCHG | CPU operating clock switch | 1 | OSC3 |
| 0 | OSC1 | 1 | R/W |
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| D1 | SOSC3 | 1 | On |
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| 0 | Off | 1 | R/W |
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| D0 | SOSC1 | 1 | On |
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| 0 | Off | 1 | R/W |
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Prescaler clock | 0040181 | – | reserved |
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| – |
| 0 | – |
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select register | (B) | D0 | PSCDT0 | Prescaler clock selection | 1 | OSC1 |
| 0 | OSC3/PLL | 0 | R/W |
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Power control | 004019E | D7 | CLGP7 | Power control register protect flag | Writing 10010110 (0x96) | 0 | R/W |
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protect register | (B) | D6 | CLGP6 |
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| removes the write protection of | 0 |
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| D5 | CLGP5 |
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| the power control register | 0 |
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| D4 | CLGP4 |
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| (0x40180) and the clock option | 0 |
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| D3 | CLGP3 |
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| register (0x40190). |
| 0 |
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| D2 | CLGP2 |
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| Writing another value set the | 0 |
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| D1 | CLGP1 |
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| write protection. |
| 0 |
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| D0 | CLGP0 |
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| 0 |
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PSCON: Prescaler on/off control (D5) / Power control register (0x40180)
Turns the prescaler on or off.
Write "1": On
Write "0": Off
Read: Valid
The source clock is input to the prescaler by writing "1" to PSCON, thereby starting a dividing operation.
The prescaler is turned off by writing "0". If the peripheral circuits do not need to be operated, write "0" to this bit to reduce current consumption. Since PSCON is protected against writing the same as SOSC1, SOSC3, CLKCHG and CLKDT[1:0], CLGP[7:0] must be set to "0b10010110" before PSCON can be changed.
At initial reset, PSCON is set to "1" (On).
Note that when PSCON is set to "0" (Off), the source clock supplied to the prescaler is stopped. This means that PSCON must not be set to "0" (Off) if any of the peripheral circuits (including the serial interface and ports) that use the clock supplied to the prescaler are in use.
S1C33210 FUNCTION PART | EPSON |