II CORE BLOCK: BCU (Bus Control Unit)

SRAM Write Cycles

Basic write cycle with no wait mode

C1

C2

BCLK

 

A[23:0]

addr

#CExx

 

D[15:0]

data

#WRH/#WRL

 

#WAIT

 

#WR

#BSL/#BSH

Figure 4.22 Half-word Write Cycle with No Wait

C1

C2

C3

C4

BCLK

 

 

 

A[23:0]

 

addr

 

#CExx

 

 

 

#WRH

 

 

 

#WRL

 

 

 

D[15:8]

Undefined

 

Valid

D[7:0]

Valid

 

Undefined

Figure 4.23 Byte Write Cycle with No Wait (A0 system, little endian)

C1

C2

C3

C4

BCLK

 

 

 

A[23:0]

 

addr

 

#CExx

 

 

 

#BSH

 

 

 

#BSL

 

 

 

#WRL

 

 

 

D[15:8]

Undefined

 

Valid

D[7:0]

Valid

 

Undefined

Figure 4.24 Byte Write Cycle with No Wait (#BSL system, little endian)

B-II-4-20

EPSON

S1C33210 FUNCTION PART