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| 4 | PERIPHERAL CIRCUITS | ||
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Register name | Address | Bit | Name | Function |
| Setting |
| Init. | R/W | Remarks | |||
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HDLC residue | 0200332 | – | – |
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| – |
| – | – | 0 when being read. | ||
code register | (HW) | D7 | RCODE7 | Residue Code | RCODE[7:0] |
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| Effective bits | X | R | Only valid when | ||
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| D6 | RCODE6 | Number of valid bits in excess | 11111110 |
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| 7 | X |
| RESID = 1 | |
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| D5 | RCODE5 | residue code bits at end of frame | 11111100 |
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| 6 | X |
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| D4 | RCODE4 |
| 11111000 |
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| 5 | X |
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| D3 | RCODE3 |
| 11110000 |
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| 4 | X |
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| D2 | RCODE2 |
| 11100000 |
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| 3 | X |
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| D1 | RCODE1 |
| 11000000 |
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| 2 | X |
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| D0 | RCODE0 |
| 10000000 |
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| 1 | X |
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HDLC transmit | 0200334 | – | – |
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| – |
| – | – | 0 when being read. | ||
status register | (HW) | D7 | TXUE | Tx underrun/EOM detected | 1 | Yes |
| 0 | No | X | R |
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| D6 | TXBRDY | Transmit queue not full | 1 | not Full |
| 0 | Full | X | R |
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| – | – |
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| – |
| – | – | 0 when being read. | ||
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| D0 | TXUDR | Transmit queue underrun | 1 | Under run |
| 0 | No underrun | X | R |
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HDLC monitor | 0200336 | – | – |
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| – |
| – | – | 0 when being read. | ||
register | (HW) | D7 | ESINT | E/S INT interrupt | 1 | Request pending |
| 0 | No interrupts | X | R |
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| D6 | SPINT | Sp INT interrupt | 1 | Request pending |
| 0 | No interrupts | X | R |
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| D5 | RXINT | Rx INT interrupt | 1 | Request pending |
| 0 | No interrupts | X | R |
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| D4 | TXINT | Tx INT interrupt | 1 | Request pending |
| 0 | No interrupts | X | R |
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| – | – |
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| – |
| – | – | 0 when being read. | ||
S1C33210 PRODUCT PART | EPSON |