III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
TXFTH[1:0]: HDLC transmit queue interrupt threshold (D[1:0]) / HDLC transmit queue threshold register (0x020031A)
These bits specify the level triggering transmit queue interrupts: from 0 for completely empty to 3 for at least one slot free.
RTXUEL: HDLC reset Tx underrun/EOM latch (D7) / HDLC transmit control register (0x020031C)
SNDABT: HDLC send Abort (D6) / HDLC transmit control register (0x020031C)
TXFR: HDLC transmit queue reset (D5) / HDLC transmit control register (0x020031C)
RTXU: HDLC reset Tx underrun (D0) / HDLC transmit control register (0x020031C)
Writing "1" to a bit issues the corresponding HDLC transmit control command. Note that there is a new command for each such write. Writes of "0" are ignored.
Writing "1" to RTXUEL resets the Tx underrun/EOM latch. Sending a CRC at the end of a frame requires issuing this command before an underrun. This command is only valid when transmit operation is enabled.
Write "1": Reset Tx Underrun/EOM Latch
Write "0": Invalid
Writing "1" to SNDABT sends an abort pattern (eight "1" bits), sets the Tx underrun/EOM bit to "1," and clears the transmit queue. Note that this command sends the abort pattern immediately. There is no wait for a byte boundary.
Write "1": Send Abort
Write "0": Invalid
Writing "1" to TXFR clears the transmit queue to empty. Any data there is lost.
Write "1": Tx FIFO Reset
Write "0": Invalid
Writing "1" to RTXU resets the TXUDR underrun flag (D0/0x0200334, HDLC transmit status register) to "0."
Write "1": Reset Tx Underrun
Write "0": Invalid
TXD[7:0]: HDLC transmit data (D[7:0]) / HDLC transmit data register (0x020031E)
This
Reads return indeterminate values. The HDLC interface transmits the LSB (bit 0) first.
TXUE: HDLC Tx underrun/EOM (D7) / HDLC transmit status register (0x0200334)
TXBRDY: HDLC transmit buffer ready (D6) / HDLC transmit status register (0x0200334)
TXUDR: HDLC Tx underrun (D0) / HDLC transmit status register (0x0200334)
These bits give the HDLC transmit operation status.
A "1" in TXUE indicates an empty transmit queue (underrun/EOM) during or after a frame. The transition from "0" to "1" forces transmission of a CRC or abort pattern as specified by the CRC/Abort on underrun/EOM bit in the HDLC transmit operation settings register (D1/0x0200318). If the bit is already "1," the hardware skips this step. The hardware then sends a closing flag pattern. Note that sending a CRC or abort pattern before the closing flag pattern requires resetting this bit to "0" with a reset Tx underrun/OEM latch command (D7/0x020031C).
This bit also goes to "1" after a disable transmit or send abort (D6/0x020031C) command. The reverse transition, from "1" to "0," produces an E/S INT interrupt.
This bit is the same as TXUE in the HDLC E/S INT receive status register (D5/0x020032C).
A "1" in TXBRDY indicates that the transmit queue is not full. Note, however, that this bit transition does not necessarily match the interrupts because interrupt timing depends on such factors as interrupt mode and queue interrupt threshold.
TXUDR goes to "1" when the hardware reads from an empty queue. It differs from TXUE above in that it merely indicates the status and does not trigger an interrupt request. To clear this bit, write "1" to RTXU in the HDLC transmit control register (D0/0x020031C).
EPSON | S1C33210 FUNCTION PART |