
8 ELECTRICAL CHARACTERISTICS
Common characteristics
| (Unless otherwise specified: VDD=2.7V to 3.6V, VSS=0V, | ° C) | ||||||
Item |
| Symbol | Min. | Max. | Unit |
| ∗ |
|
Address delay time |
| tAD | – | 10 | ns |
| 1 |
|
#CEx delay time (1) |
| tCE1 | – | 10 | ns |
|
|
|
#CEx delay time (2) |
| tCE2 | – | 10 | ns |
|
|
|
Wait setup time |
| tWTS | 17 | – | ns |
|
|
|
Wait hold time |
| tWTH | 0 | – | ns |
|
|
|
Read signal delay time (1) |
| tRDD1 |
| 10 | ns |
| 2 |
|
Read data setup time |
| tRDS | 15 |
| ns |
|
|
|
Read data hold time |
| tRDH | 0 |
| ns |
|
|
|
Write signal delay time (1) |
| tWRD1 |
| 10 | ns |
| 3 |
|
Write data delay time (1) |
| tWDD1 |
| 10 | ns |
|
|
|
Write data delay time (2) |
| tWDD2 | 0 | 10 | ns |
|
|
|
Write data hold time |
| tWDH | 0 |
| ns |
|
|
|
∗note 1) This applies to the #BSH and #BSL timings.
2)This applies to the #GAAS and #GARD timings.
3)This applies to the #GAAS timing.
SRAM read cycle
(Unless otherwise specified: VDD=2.7V to 3.6V, VSS=0V,
Item | Symbol | Min. | Max. | Unit | ∗ |
Read signal delay time (2) | tRDD2 |
| 10 | ns |
|
Read signal pulse width | tRDW |
| ns |
| |
Read address access time (1) | tACC1 |
| ns |
| |
Chip enable access time (1) | tCEAC1 |
| ns |
| |
Read signal access time (1) | tRDAC1 |
| ns |
|
SRAM write cycle
| (Unless otherwise specified: VDD=2.7V to 3.6V, VSS=0V, | ° C) | ||||||
Item |
| Symbol | Min. | Max. | Unit |
| ∗ |
|
Write signal delay time (2) |
| tWRD2 |
| 10 | ns |
|
|
|
Write signal pulse width |
| tWRW |
| ns |
|
|
|
EPSON | S1C33210 PRODUCT PART |