III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
Selecting input pins
For the FPK1 interrupt system, a
Table 9.7 shows the control bits and the selectable groups for each factor.
Table 9.7 Selecting Pins for Key Input Interrupts
Interrupt | Control bit |
| SPPK settings |
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| 11 | 10 | 01 | 00 |
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FPK1 | SPPK1[1:0] (D[3:2])/Key input interrupt select register (0x402CA) | P2[7:4] | P0[5:4] | CP[3:0] | K6[3:0] |
FPK0 | SPPK0[1:0] (D[1:0])/Key input interrupt select register (0x402CA) | P2[4:0] | P0[4:0] | K6[3:0] | K5[2:0] |
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| CP0 | CP4 |
Conditions for key
The key input interrupt circuit has two input mask registers (SMPK0[4:0] for FPK0 and SMPK1[3:0] for FPK1) and two input comparison registers (SCPK0[4:0] for FPK0 and SCPK0[3:0] for FPK1) to set
The input mask register SMPK is used to mask the input pin that is not used for an interrupt. This register masks each input pin, whereas the interrupt enable register of the interrupt controller masks the interrupt factor for each interrupt group.
The input comparison register SCPK is used to select whether an interrupt for each input port is to be generated at the rising or falling edge of the input.
Achange in state occurs so that the input pin enabled for interrupt by the interrupt mask register SMPK and the content of the input comparison register SCPK become unmatched after being matched, the interrupt factor flag FK is set to "1" and, if other interrupt conditions are met, an interrupt is generated.
Figure 9.5 shows cases in which a FPK0 interrupt is generated. Here, it is assumed that the K5[4:0] pins are selected for the
Intput mask register SMPK0
SMPK04 SMPK03 SMPK02 SMPK01 SMPK00
1 | 1 | 1 | 1 | 0 |
Input comparison register SCPK0
SCPK04 SCPK03 SCPK02 SCPK01 SCPK00
1 | 1 | 0 | 1 | 0 |
With the settings shown above, FPK0 interrupt is generated under the condition shown below.
Input port K5
(1) | – | CP4 | K52 | K51 | K50 |
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| 1 | 1 | 0 | 1 | 0 |
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(2) |
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– | CP4 | K52 | K51 | K50 |
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| 1 | 1 | 0 | 1 | 1 |
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(3) |
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– | CP4 | K52 | K51 | K50 |
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| 1 | 0 | 0 | 1 | 0 |
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| Because interrupt has been disabled for |
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(4) |
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| K50, interrupt will be generated when non- |
– | CP4 | K52 | K51 | K50 |
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| 1 | 0 | 1 | 1 | 0 |
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| the four bits K51, K52, CP4 and the four | |
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| bits input comparison register SCPK0[4:1]. |
Figure 9.5 FPK0 Interrupt Generation Example (when K5[2:0] and CP4 are selected by SPPK[1:0])
EPSON | S1C33210 FUNCTION PART |