II CORE BLOCK: BCU (Bus Control Unit)

 

 

 

Area

Address

 

 

 

Area 17+18 (#CE17+18)

0xFFFFFFF

(Mirror of External memory 7')

 

 

SRAM type

 

 

0xD000000

 

 

 

8 or 16 bits

0xCFFFFFF

External memory 7' (16MB)

 

 

 

0xC000000

 

 

 

 

 

 

 

0xBFFFFFF

(Mirror of External memory 7)

 

 

 

0x9000000

 

 

 

 

0x8FFFFFF

External memory 7 (16MB)

 

 

 

0x8000000

 

 

 

 

 

 

Areas 15–16 (#CE15+16)

0x7FFFFFF

(Mirror of External memory 6')

 

 

SRAM type

 

 

0x7000000

 

 

 

8 or 16 bits

0x6FFFFFF

External memory 6' (16MB)

 

 

 

0x6000000

 

 

 

 

 

 

 

0x5FFFFFF

(Mirror of External memory 6)

 

 

 

0x5000000

 

 

 

 

0x4FFFFFF

External memory 6 (16MB)

 

 

 

0x4000000

 

 

 

 

 

 

Area 14 (#CE14/#RAS3)

0x3FFFFFF

 

 

 

SRAM type

 

External memory 5 (16MB)

 

 

DRAM type

 

 

 

 

 

 

 

8 or 16 bits

0x3000000

 

 

 

Area 13 (#CE13/#RAS2)

0x2FFFFFF

 

 

 

SRAM type

 

External memory 4 (16MB)

 

 

DRAM type

 

 

 

 

 

 

 

8 or 16 bits

0x2000000

 

 

 

Areas 11–12 (#CE11+12)

0x1FFFFFF

 

 

 

SRAM type

 

External memory 3 (16MB)

 

 

8 or 16 bits

 

 

 

 

 

 

 

 

0x1000000

 

 

 

Areas 9–10 (#CE9+10EX)

0x0FFFFFF

 

 

 

SRAM type

 

External memory 2 (8MB)

 

 

Burst ROM type

 

 

 

 

 

 

 

8 or 16 bits

0x0800000

 

 

 

Areas 7–8 (#CE7+8)

0x07FFFFF

 

 

 

SRAM type

 

External memory 1 (4MB)

 

 

8 or 16 bits

 

 

 

 

 

 

 

 

0x0400000

 

 

CEFUNC = "10" or "11"

Figure 4.2 External System Memory Map

Furthermore, the #CE4+#CE5 and #CE6 signals can be output from the P30 and P34 terminals, respectively. This function expands the accessible area when CEFUNC is set to "01, "10" or "11".

To output the #CE4+#CE5 signal from the P30 terminal: CFP30 (D0)/P3 function select register (0x402DC) = "1" IOC30 (D0)/P3 I/O control register (0x402DE) = "1"

To output the #CE6 signal from the P34 terminal:

CFP34 (D4)/P3 function select register (0x402DC) = "1"

IOC34 (D4)/P3 I/O control register (0x402DE) = "1"

The P30 and P34 terminals are set for the general I/O ports at initial reset.

The P30 and P34 terminals are shared with the #WAIT input and the #BUSREQ input, respectively. Therefore, when using the #WAIT and #BUSREQ signals, these terminals cannot be used for #CE4+#CE5 and #CE6 outputs.

B-II-4-6

EPSON

S1C33210 FUNCTION PART