II CORE BLOCK: BCU (Bus Control Unit)
A1X1MD: Area 1 access speed (D3) / BCLK select register (0x4813A)
Select a number of access cycles for area 1 in ⋅ 2 speed mode.
Write "1": 2 cycles
Write "0": 4 cycles
Read: Valid
When ⋅ 2 speed mode is set (#X2SPD pin = L) and A1X1MD = "1", area 1 is read/written in 2 cycles of the CPU system clock.
When A1X1MD = "0", area 1 is read/written in 4 cycles.
When x1 speed mode is set (#X2SPD pin = H), area 1 is always accessed in 2 cycles regardless of the A1X1MD value.
At cold start, A1X1MD is set to "0" (4 cycles). At hot start, A1X1MD retains its status before being initialized.
Programming Notes
The S1C33210 maps the mobile access interface registers to memory area 5. Accessing these registers therefore requires setting two bits to "1": A5IO, bit 8 in the access control register (0x0048132), and SWAITE, bit 0 in the bus control register (0x0048132). The latter setting enables the internal #WAIT signal.
EPSON | S1C33210 FUNCTION PART |