III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
Register name | Address | Bit | Name | Function |
|
|
| Setting |
| Init. | R/W | Remarks | ||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
HDLC receive | 0200312 |
| – | – |
|
|
|
|
| – |
| – | – | 0 when being read. | ||
interrupt mode | (HW) | D1 | RXINTS1 | HDLC receive interrupt setup | RXINTS[1:0] | Operating Mode | 0 | R/W |
| |||||||
settings |
|
| D0 | RXINTS0 |
|
| 1 | 1 |
|
| (Not allowed) | 0 | R/W |
| ||
register |
|
|
|
|
|
| 1 | 0 | Sp INT Only |
|
|
| ||||
|
|
|
|
|
|
| 0 | 1 | Rx INT and Sp |
|
|
| ||||
|
|
|
|
|
|
|
|
|
| INT On FIFO |
|
|
| |||
|
|
|
|
|
|
|
|
|
| Threshold Level |
|
|
| |||
|
|
|
|
|
|
| 0 | 0 | Rx INT and Sp |
|
|
| ||||
|
|
|
|
|
|
|
|
|
| INT On First Rx |
|
|
| |||
|
|
|
|
|
|
|
|
|
| Character |
|
|
| |||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
HDLC receive | 0200314 |
| – | – |
|
|
|
|
| – |
| – | – | 0 when being read. | ||
control register | (HW) | D2 | RXFR | HDLC receive queue reset | 1 |
| Reset |
|
| 0 | Ignored | 0 | W |
| ||
|
|
| D1 | ENTHM | HDLC enter Hunt mode | 1 |
| Force shift |
| 0 | Ignored | 0 | W |
| ||
|
|
| D0 | RXINXT | HDLC Rx INT on next receive character | 1 |
| Specify interrupt |
| 0 | Ignored | 0 | W |
| ||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
HDLC receive | 0200316 |
| – | – |
|
|
|
|
| – |
| – | – | 0 when being read. | ||
data register | (HW) | D7 | RXD7 | HDLC receive data |
|
|
| 0x00 to 0xFF | X | R |
| |||||
|
|
| D6 | RXD6 | RXD7 = MSB |
|
|
|
|
|
|
|
| X |
|
|
|
|
| D5 | RXD5 | RXD0 = LSB |
|
|
|
|
|
|
|
| X |
|
|
|
|
| D4 | RXD4 |
|
|
|
|
|
|
|
|
| X |
|
|
|
|
| D3 | RXD3 |
|
|
|
|
|
|
|
|
| X |
|
|
|
|
| D2 | RXD2 |
|
|
|
|
|
|
|
|
| X |
|
|
|
|
| D1 | RXD1 |
|
|
|
|
|
|
|
|
| X |
|
|
|
|
| D0 | RXD0 |
|
|
|
|
|
|
|
|
| X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
HDLC transmit | 0200318 |
| – | – |
|
|
|
|
| – |
| – | – | 0 when being read. | ||
operation | (HW) | D1 | ABTCRC | HDLC CRC/Abort on underrun/EOM | 1 |
| Transmit abort |
|
| 0 | Transmit CRC | 0 | R/W |
| ||
settings |
|
|
|
|
|
|
| and flag patterns |
| and flag |
|
|
| |||
register |
|
| D0 | MRKFLG | HDLC Mark/Flag on idle | 1 |
| Transmit |
|
| 0 | Transmit flag | 0 | R/W |
| |
|
|
|
|
|
|
|
| mark pattern |
|
|
|
|
|
| ||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
HDLC transmit | 020031A | – | – |
|
|
|
|
| – |
| – | – | 0 when being read. | |||
queue | (HW) | D1 | TXFTH1 | HDLC transmit queue interrupt | TXFTH[1:0] |
|
|
| Level | 0 | R/W |
| ||||
threshold |
|
| D0 | TXFTH0 | threshold |
| 1 | 1 |
|
| 1 empty | 0 | R/W |
| ||
register |
|
|
|
|
|
| 1 | 0 |
|
| 2 empty |
|
|
| ||
|
|
|
|
|
|
| 0 | 1 |
|
| 3 empty |
|
|
| ||
|
|
|
|
|
|
| 0 | 0 |
|
| All 4 empty |
|
|
| ||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
HDLC transmit | 020031C | – | – |
|
|
|
|
| – |
| – | – | 0 when being read. | |||
control register | (HW) | D7 | RTXUEL | HDLC reset Tx underrun/EOM latch | 1 |
| Reset latch |
|
| 0 | Ignored | 0 | W | Writes of "0" are ignored | ||
|
|
| D6 | SNDABT | HDLC sent Abort | 1 |
| Transmit |
|
| 0 | Ignored | 0 | W | Writes of "0" are ignored | |
|
|
|
|
|
|
|
| abort pattern |
|
|
|
|
|
| ||
|
|
| D5 | TXFR | HDLC transmit queue reset | 1 |
| Reset queue |
| 0 | Ignored | 0 | W | Writes of "0" are ignored | ||
|
|
| – | – |
|
|
|
|
| – |
| – | – | 0 when being read. | ||
|
|
| D0 | RTXU | HDLC reset Tx underrun | 1 |
| Reset flag |
|
| 0 | Ignored | 0 | W | Writes of "0" are ignored | |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
HDLC transmit | 020031E | – | – |
|
|
|
|
| – |
| – | – | Indeterminate value | |||
data register | (HW) |
|
|
|
|
|
|
|
|
|
|
|
|
| when read | |
|
|
| D7 | TXD7 | HDLC transmit data |
|
|
| 0x00 to 0xFF | X | W | Indeterminate value | ||||
|
|
| D6 | TXD6 | TXD7 = MSB |
|
|
|
|
|
|
|
| X |
| when read |
|
|
| D5 | TXD5 | TXD0 = LSB |
|
|
|
|
|
|
|
| X |
|
|
|
|
| D4 | TXD4 |
|
|
|
|
|
|
|
|
| X |
|
|
|
|
| D3 | TXD3 |
|
|
|
|
|
|
|
|
| X |
|
|
|
|
| D2 | TXD2 |
|
|
|
|
|
|
|
|
| X |
|
|
|
|
| D1 | TXD1 |
|
|
|
|
|
|
|
|
| X |
|
|
|
|
| D0 | TXD0 |
|
|
|
|
|
|
|
|
| X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
HDLC E/S INT | 020032C | – | – |
|
|
|
|
| – |
| – | – | 0 when being read. | |||
receive status | (HW) | D7 | ABORT | HDLC Abort detected | 1 |
| Detected |
|
| 0 | Not detected | X | R |
| ||
register |
|
| D6 | – | – |
|
|
|
|
| – |
| – | – | 0 when being read. | |
|
|
| D5 | TXUE | HDLC Tx underrun/EOM detected | 1 |
| Detected |
|
| 0 | Not detected | X | R |
| |
|
|
| – | – |
|
|
|
|
| – |
| – | – | 0 when being read. | ||
|
|
| D1 | HUNT | HDLC Hunt detected | 1 |
| Hunting |
|
| 0 | Not hunting | X | R |
| |
|
|
| D0 | IDLED | HDLC Idle detected | 1 |
| Detected |
|
| 0 | Not detected | X | R |
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
HDLC Sp INT | 020032E | – | – |
|
|
|
|
| – |
| – | – | 0 when being read. | |||
receive status | (HW) | D7 | RXOVR | HDLC Rx overrun detected | 1 |
| Detected |
|
| 0 | Not detected | X | R |
| ||
register |
|
| D6 | EOF | HDLC end of frame detected | 1 |
| Detected |
|
| 0 | Not detected | X | R |
| |
|
|
| – | – |
|
|
|
|
| – |
| – | – | 0 when being read. | ||
|
|
| D0 | SHFD | HDLC short frame detected | 1 |
| Detected |
|
| 0 | Not detected | X | R |
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
HDLC receive | 0200330 |
| – | – |
|
|
|
|
| – |
| – | – | 0 when being read. | ||
status register | (HW) | D2 | RESID | HDLC residue detected | 1 |
| Detected |
|
| 0 | Not detected | X | R |
| ||
|
|
| D1 | RCA | HDLC receive character available | 1 |
| Available |
|
| 0 | Not available | X | R |
| |
|
|
| D0 | CRCER | HDLC CRC error detected | 1 |
| Detected |
|
| 0 | Not detected | X | R |
|
EPSON | S1C33210 FUNCTION PART |