II CORE BLOCK: ITC (Interrupt Controller)

Register name

Address

Bit

Name

Function

 

 

Setting

 

Init.

R/W

Remarks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16-bit timer 4/5

0040268

D7

–

reserved

 

 

–

 

–

–

0 when being read.

interrupt

(B)

D6

P16T52

16-bit timer 5 interrupt level

 

 

0 to 7

 

X

R/W

 

priority register

 

D5

P16T51

 

 

 

 

 

 

 

X

 

 

 

 

D4

P16T50

 

 

 

 

 

 

 

X

 

 

 

 

D3

–

reserved

 

 

–

 

–

–

0 when being read.

 

 

D2

P16T42

16-bit timer 4 interrupt level

 

 

0 to 7

 

X

R/W

 

 

 

D1

P16T41

 

 

 

 

 

 

 

X

 

 

 

 

D0

P16T40

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8-bit timer,

0040269

D7

–

reserved

 

 

–

 

–

–

0 when being read.

serial I/F Ch.0

(B)

D6

PSI002

Serial interface Ch.0

 

 

0 to 7

 

X

R/W

 

interrupt

 

D5

PSI001

interrupt level

 

 

 

 

 

 

X

 

 

priority register

 

D4

PSI000

 

 

 

 

 

 

 

X

 

 

 

 

D3

–

reserved

 

 

–

 

–

–

0 when being read.

 

 

D2

P8TM2

8-bit timer 0–3 interrupt level

 

 

0 to 7

 

X

R/W

 

 

 

D1

P8TM1

 

 

 

 

 

 

 

X

 

 

 

 

D0

P8TM0

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial I/F Ch.1,

004026A

D7

–

reserved

 

 

–

 

–

–

0 when being read.

A/D interrupt

(B)

D6

PAD2

A/D converter interrupt level

 

 

0 to 7

 

X

R/W

 

priority register

 

D5

PAD1

 

 

 

 

 

 

 

X

 

 

 

 

D4

PAD0

 

 

 

 

 

 

 

X

 

 

 

 

D3

–

reserved

 

 

–

 

–

–

0 when being read.

 

 

D2

PSI012

Serial interface Ch.1

 

 

0 to 7

 

X

R/W

 

 

 

D1

PSI011

interrupt level

 

 

 

 

 

 

X

 

 

 

 

D0

PSI010

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock timer

004026B

D7–3

–

reserved

 

 

–

 

–

–

Writing 1 not allowed.

interrupt

(B)

D2

PCTM2

Clock timer interrupt level

 

 

0 to 7

 

X

R/W

 

priority register

 

D1

PCTM1

 

 

 

 

 

 

 

X

 

 

 

 

D0

PCTM0

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port input 4/5

004026C

D7

–

reserved

 

 

–

 

–

–

0 when being read.

interrupt

(B)

D6

PP5L2

Port input 5 interrupt level

 

 

0 to 7

 

X

R/W

 

priority register

 

D5

PP5L1

 

 

 

 

 

 

 

X

 

 

 

 

D4

PP5L0

 

 

 

 

 

 

 

X

 

 

 

 

D3

–

reserved

 

 

–

 

–

–

0 when being read.

 

 

D2

PP4L2

Port input 4 interrupt level

 

 

0 to 7

 

X

R/W

 

 

 

D1

PP4L1

 

 

 

 

 

 

 

X

 

 

 

 

D0

PP4L0

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port input 6/7

004026D

D7

–

reserved

 

 

–

 

–

–

0 when being read.

interrupt

(B)

D6

PP7L2

Port input 7 interrupt level

 

 

0 to 7

 

X

R/W

 

priority register

 

D5

PP7L1

 

 

 

 

 

 

 

X

 

 

 

 

D4

PP7L0

 

 

 

 

 

 

 

X

 

 

 

 

D3

–

reserved

 

 

–

 

–

–

0 when being read.

 

 

D2

PP6L2

Port input 6 interrupt level

 

 

0 to 7

 

X

R/W

 

 

 

D1

PP6L1

 

 

 

 

 

 

 

X

 

 

 

 

D0

PP6L0

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Key input,

0040270

D7–6

–

reserved

 

 

–

 

–

–

0 when being read.

port input 0–3

(B)

D5

EK1

Key input 1

1

Enabled

 

0

 

Disabled

0

R/W

 

interrupt

 

D4

EK0

Key input 0

 

 

 

 

 

 

0

R/W

 

enable register

 

D3

EP3

Port input 3

 

 

 

 

 

 

0

R/W

 

 

 

D2

EP2

Port input 2

 

 

 

 

 

 

0

R/W

 

 

 

D1

EP1

Port input 1

 

 

 

 

 

 

0

R/W

 

 

 

D0

EP0

Port input 0

 

 

 

 

 

 

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DMA interrupt

0040271

D7–5

–

reserved

 

 

–

 

–

–

0 when being read.

enable register

(B)

D4

EIDMA

IDMA

1

Enabled

 

0

 

Disabled

0

R/W

 

 

 

D3

EHDM3

High-speed DMA Ch.3

 

 

 

 

 

 

0

R/W

 

 

 

D2

EHDM2

High-speed DMA Ch.2

 

 

 

 

 

 

0

R/W

 

 

 

D1

EHDM1

High-speed DMA Ch.1

 

 

 

 

 

 

0

R/W

 

 

 

D0

EHDM0

High-speed DMA Ch.0

 

 

 

 

 

 

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16-bit timer 0/1

0040272

D7

E16TC1

16-bit timer 1 comparison A

1

Enabled

 

0

 

Disabled

0

R/W

 

interrupt

(B)

D6

E16TU1

16-bit timer 1 comparison B

 

 

 

 

 

 

0

R/W

 

enable register

 

D5–4

–

reserved

 

 

–

 

–

–

0 when being read.

 

 

D3

E16TC0

16-bit timer 0 comparison A

1

Enabled

 

0

 

Disabled

0

R/W

 

 

 

D2

E16TU0

16-bit timer 0 comparison B

 

 

 

 

 

 

0

R/W

 

 

 

D1–0

–

reserved

 

 

–

 

–

–

0 when being read.

 

 

 

 

 

 

 

 

 

 

 

 

 

16-bit timer 2/3

0040273

D7

E16TC3

16-bit timer 3 comparison A

1

Enabled

 

0

 

Disabled

0

R/W

 

interrupt

(B)

D6

E16TU3

16-bit timer 3 comparison B

 

 

 

 

 

 

0

R/W

 

enable register

 

D5–4

–

reserved

 

 

–

 

–

–

0 when being read.

 

 

D3

E16TC2

16-bit timer 2 comparison A

1

Enabled

 

0

 

Disabled

0

R/W

 

 

 

D2

E16TU2

16-bit timer 2 comparison B

 

 

 

 

 

 

0

R/W

 

 

 

D1–0

–

reserved

 

 

–

 

–

–

0 when being read.

S1C33210 FUNCTION PART

EPSON

B-II-5-13