III PERIPHERAL BLOCK: SERIAL INTERFACE

Setting Clock-Synchronized Interface

When performing clock-synchronized transfers via the serial interface, the following settings must be made before data transfer is actually begun:

1.Setting input/output pins

2.Setting the interface mode

3.Setting the transfer mode

4.Setting the input clock

5.Setting interrupts and IDMA/HSDMA

The following explains the content of each setting. For details on interrupt/DMA settings, refer to "Serial Interface Interrupts and DMA".

Note: Always make sure the serial interface is inactive (TXENx and RXENx = "0") before these settings are made. A change of settings during operation may cause a malfunction.

Setting input/output pins

All four pins—SINx, SOUTx, #SCLKx, and #SRDYx—are used in the clock-synchronized mode. When using Ch.0, set CFP0[3:0] (D[3:0]) / P0 function select register (0x402D0) to "1111" and when using Ch.2, set D[3:0]

/Port SIO function extension register (0x402DB) to "1111". (It is possible to use both channels.)

Note: Ch. 1 and Ch. 3 support only asynchronous operation.

Setting the interface mode

IRMDx[1:0] (D[1:0]) / Serial I/F Ch.0 IrDA register (0x401E4) or Serial I/F Ch.2 IrDA register (0x401F4) is used to set the interface mode (normal or IrDA interface). Write "00" to IRMDx[1:0] to choose the ordinary interface. Since IRMDx[1:0] becomes indeterminate at initial reset, it must be initialized.

Setting the transfer mode

Use SMDx to set the transfer mode of the serial interface as described earlier.When using the serial interface as the master for clock-synchronized transfer, set SMDx[1:0] to "00"; when using the serial interface as a slave, set SMDx[1:0] to "01".

Setting the input clock

•Clock-synchronized master mode

This mode operates using an internally derived clock. The clock source for each channel is as follows: Ch.0: A clock output by 8-bit programmable timer 2

Ch.1: A clock output by 8-bit programmable timer 3

Ch.2: A clock output by 8-bit programmable timer 4

Ch.3: A clock output by 8-bit programmable timer 5

Therefore, in order for the serial interface to be used in the clock-synchronized master mode, the following conditions must be met:

1.The prescaler is feeding a clock to 8-bit programmable timer 2 (3).

2.The 8-bit programmable timer 2 (3) is generating a clock.

Any desired clock frequency can be selected by setting the division ratio of the prescaler and the reload data of the 8-bit programmable timer as necessary. The relationship between the contents of these settings and the transfer rate is expressed by Eq. 1 below.

To ensure that the duty ratio of the clock to be fed to the serial interface is 50%, the 8-bit programmable timer further divides the underflow signal frequency by 2 internally. This 1/2 frequency division is factored into Eq. 1.

S1C33210 FUNCTION PART

EPSON

B-III-8-5