III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES

I/O Memory for Mobile Access Interfaces

Table 10.11 lists the contents of the I/O memory for mobile access interfaces.

Table 10.11 I/O Memory for Mobile Access Interfaces

Register name

Address

Bit

Name

Function

 

 

 

 

Setting

 

Init.

R/W

Remarks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Communications

0200000

D15–2

–

–

 

 

 

 

 

 

–

 

–

–

0 when being read.

macro select

(HW)

D1

MCRS1

Communications macro select

MCRS[1:0]

 

Communications mode

0

R/W

Only valid when

register

 

D0

MCRS0

 

1

 

 

1

 

 

 

 

 

PHS

0

 

MSEL pin input is at

 

 

 

 

 

1

 

 

0

 

 

 

 

 

PDC

 

 

High level

 

 

 

 

 

0

 

 

1

 

 

 

 

 

HDLC

 

 

 

 

 

 

 

 

0

 

 

0

 

 

 

 

 

UART

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Software reset

0200002

D15–3

–

–

 

 

 

 

 

 

–

 

–

–

0 when being read.

register

(HW)

D2

PHSRST

PHS block reset

1

Reset

 

0

 

Invalid

0

W

 

 

 

D1

PDCRST

PDC block reset

1

Reset

 

0

 

Invalid

0

W

 

 

 

D0

HDLRST

HDLC block reset

1

Reset

 

0

 

Invalid

0

W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Communications

0200004

D15-4

–

–

 

 

 

 

 

 

–

 

–

–

0 when being read.

block clock

(HW)

D3

CKD3

Clock frequency divider

 

 

CKD[3:0]

 

 

 

 

Frequency

1

R/W

fout = PERICLK

frequency

 

D2

CKD2

 

1

 

1

1

 

1

 

 

fout/16

1

R/W

output

divider register

 

D1

CKD1

 

1

 

1

1

 

0

 

 

fout/15

1

R/W

frequency

 

 

D0

CKD0

 

1

 

1

0

 

1

 

 

fout/14

1

R/W

 

 

 

 

 

 

1

 

1

0

 

0

 

 

fout/13

 

 

 

 

 

 

 

 

1

 

0

1

 

1

 

 

fout/12

 

 

 

 

 

 

 

 

1

 

0

1

 

0

 

 

fout/11

 

 

 

 

 

 

 

 

1

 

0

0

 

1

 

 

fout/10

 

 

 

 

 

 

 

 

1

 

0

0

 

0

 

 

fout/9

 

 

 

 

 

 

 

 

0

 

1

1

 

1

 

 

fout/8

 

 

 

 

 

 

 

 

0

 

1

1

 

0

 

 

fout/7

 

 

 

 

 

 

 

 

0

 

1

0

 

1

 

 

fout/6

 

 

 

 

 

 

 

 

0

 

1

0

 

0

 

 

fout/5

 

 

 

 

 

 

 

 

0

 

0

1

 

1

 

 

fout/4

 

 

 

 

 

 

 

 

0

 

0

1

 

0

 

 

fout/3

 

 

 

 

 

 

 

 

0

 

0

0

 

1

 

 

fout/2

 

 

 

 

 

 

 

 

0

 

0

0

 

0

 

 

fout/2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Communications

020000A

D15–4

–

–

 

 

 

 

 

 

–

 

–

–

0 when being read.

block output port

(HW)

D3

MOPORT3

RTS output level

1

RTS="L"

 

0

 

RTS="H"

1

R/W

Only valid for PHS, PDC,

data register

 

D2

MOPORT2

DTR output level

1

DTR="L"

 

0

 

DTR="H"

1

R/W

and HDLC operation

 

 

D1

CNT2

CNT2 output level

1

CNT2="L"

 

0

 

CNT2="H"

1

R/W

Always valid

 

 

D0

CNT1

CNT1 output level

1

CNT1="L"

 

0

 

CNT1="H"

1

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Communications

020000C

D15–8

–

–

 

 

 

 

 

 

–

 

–

–

0 when being read.

block input port

(HW)

D7

GOUTE

GOUT output enable

1

Enable

 

0

 

Disable

0

R/W

 

data register

 

D6–2

–

–

 

 

 

 

 

 

–

 

–

–

0 when being read.

 

 

D1

MIPORT1

DSR input level

1

DSR="H"

 

0

 

DSR="L"

X

R

 

 

 

D0

MIPORT0

RI input level

1

RI="H"

 

0

 

RI="L"

X

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Communications

0200010

D15–3

–

–

 

 

 

 

 

 

–

 

–

–

0 when being read.

block PHS mode

(HW)

D2

BMODE

Data conversion switch

1

Convert

 

 

0

 

Pass through

0

R/W

 

settings register

 

D1

BHALF

Speed switch for data conversion

1

32kbps

 

 

0

 

64kbps

0

R/W

 

 

 

D0

FMODE

Frame frequency division switch

1

Frequency divider

 

0

 

Pass through

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Communications

0200020

D15–5

–

–

 

 

 

 

 

 

–

 

–

–

0 when being read.

block CP0

(HW)

D4

CP0EN4

Assign UINT4 to CP0

1

Enable

 

0

 

Disable

0

R/W

CP0= CP0EN4*UINT4

interrupt select

 

D3

CP0EN3

Assign UINT3 to CP0

1

Enable

 

0

 

Disable

0

R/W

+CP0EN3*UINT3

register

 

D2

CP0EN2

Assign UINT2 to CP0

1

Enable

 

0

 

Disable

0

R/W

+CP0EN2*UINT2

 

 

D1

CP0EN1

Assign UINT1 to CP0

1

Enable

 

0

 

Disable

0

R/W

+CP0EN1*UINT1

 

 

D0

CP0EN0

Assign UINT0 to CP0

1

Enable

 

0

 

Disable

0

R/W

+CP0EN0*UINT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Communications

0200022

D15–5

–

–

 

 

 

 

 

 

–

 

–

–

0 when being read.

block CP1

(HW)

D4

CP1EN4

Assign UINT4 to CP1

1

Enable

 

0

 

Disable

0

R/W

CP1= CP1EN4*UINT4

interrupt select

 

D3

CP1EN3

Assign UINT3 to CP1

1

Enable

 

0

 

Disable

0

R/W

+CP1EN3*UINT3

register

 

D2

CP1EN2

Assign UINT2 to CP1

1

Enable

 

0

 

Disable

0

R/W

+CP1EN2*UINT2

 

 

D1

CP1EN1

Assign UINT1 to CP1

1

Enable

 

0

 

Disable

0

R/W

+CP1EN1*UINT1

 

 

D0

CP1EN0

Assign UINT0 to CP1

1

Enable

 

0

 

Disable

0

R/W

+CP1EN0*UINT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Communications

0200024

D15–5

–

–

 

 

 

 

 

 

–

 

–

–

0 when being read.

block CP2

(HW)

D4

CP2EN4

Assign UINT4 to CP2

1

Enable

 

0

 

Disable

0

R/W

CP2= CP2EN4*UINT4

interrupt select

 

D3

CP2EN3

Assign UINT3 to CP2

1

Enable

 

0

 

Disable

0

R/W

+CP2EN3*UINT3

register

 

D2

CP2EN2

Assign UINT2 to CP2

1

Enable

 

0

 

Disable

0

R/W

+CP2EN2*UINT2

 

 

D1

CP2EN1

Assign UINT1 to CP2

1

Enable

 

0

 

Disable

0

R/W

+CP2EN1*UINT1

 

 

D0

CP2EN0

Assign UINT0 to CP2

1

Enable

 

0

 

Disable

0

R/W

+CP2EN0*UINT0

S1C33210 FUNCTION PART

EPSON

B-III-10-21