II CORE BLOCK: BCU (Bus Control Unit)
SWAITE: #WAIT enable (D0) / Bus control register (0x4812E)
Enable or disable wait cycle control via the #WAIT pin.
Write "1": Enabled
Write "0": Disabled
Read: Valid
A wait request from an SRAM device is made acceptable by writing "1" to SWAITE. The wait request signal input from the #WAIT pin is sampled at each falling edge of the bus clock when executing an SRAM read/write cycle.Wait cycles are inserted until the wait request signal is sampled and detected as high (inactive).
Wait control for 0 to 7 cycles can be accomplished by AxxWT without using the #WAIT pin. However, since the setting via AxxWT is applied to every two areas, the number of wait cycles may be controlled individually in each area or more than 7 wait cycles may be set. In such a case, use an external wait request via the #WAIT pin.
Wait requests from the #WAIT pin are ignored when SWAITE = "0".
The contents set here are applied to all areas that are set for SRAM, and are also effective for write cycles in the areas that are set for burst ROM.
At cold start, SWAITE is set to "0" (disabled). At hot start, SWAITE retains its status before being initialized.
Change the #CE
Table 4.25 #CE Output Assignment
Pin | CEFUNC = "00" | CEFUNC = "01" | CEFUNC = "1x" |
#CE4 | #CE4 | #CE11 | #CE11+#CE12 |
#CE5 | #CE5 | #CE15 | #CE15+#CE16 |
#CE6 | #CE6 | #CE6 | #CE7+#CE8 |
#CE7/#RAS0 | #CE7/#RAS0 | #CE13/#RAS2 | #CE13/#RAS2 |
#CE8/#RAS1 | #CE8/#RAS1 | #CE14/#RAS3 | #CE14/#RAS3 |
#CE9 | #CE9 | #CE17 | #CE17+#CE18 |
#CE10EX | #CE10EX | #CE10EX | #CE9+#CE10EX |
(Default: CEFUNC = "00")
The
At cold start, CEFUNC is set to "00". At hot start, CEFUNC retains its status before being initialized.
EPSON | S1C33210 FUNCTION PART |