V DMA BLOCK: HSDMA
Setting the Registers in
Make sure that the HSDMA channel is disabled (HSx_EN = "0") before seffing the control information.
Address mode
The address mode select bit DUALMx should be set to "0"
Transfer mode
A transfer mode should be set using the DxMOD[1:0] bits.
• Single transfer mode | (DxMOD = "00", default) |
• Successive transfer mode (DxMOD = "01") | |
• Block transfer mode | (DxMOD = "10") |
Refer to the explanation in "Setting the Registers in
Direction of transfer
The direction of data transfer should be set using DxDIR.
D0DIR: Ch. 0 transfer direction control (DE) / HSDMA Ch. 0 control register (0x48222)
D1DIR: Ch. 1 transfer direction control (DE) / HSDMA Ch. 1 control register (0x48232)
D2DIR: Ch. 2 transfer direction control (DE) / HSDMA Ch. 2 control register (0x48242)
D3DIR: Ch. 3 transfer direction control (DE) / HSDMA Ch. 3 control register (0x48252)
Memory write operations (data transfer from I/O device to memory) are specified by writing "1" and memory read operations (data transfer from memory to I/O device) are specified by writing "0".
Transfer data size
The DATSIZEx bit is used to set the unit size of data to be transferred.
A
Block length
When using block transfer mode (DxMOD = "10"), the data block length (in units of DATSIZEx) should be set using the BLKLENx[7:0] bits.
In single transfer and successive transfer modes, BLKLENx[7:0] is used as the
Transfer counter
Block transfer mode
In block transfer mode, up to 16 bits of transfer count can be specified using TCx_L[7:0] and TCx_H[7:0].
Single transfer and successive transfer modes
In single transfer and successive transfer modes, up to 24 bits of transfer count can be specified using BLKLENx[7:0], TCx_L[7:0] and TCx_H[7:0].
Memory address
In
In
EPSON | S1C33210 FUNCTION PART |