III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS

CFP13–CFP10: P1[3:0] pin function selection (D[3:0]) / P1 function select register (0x402D4)

Selects the pin that is used to output a timer underflow signal to external devices.

Write "1": Underflow signal output pin

Write "0": I/O port pin

Read: Valid

Select the pin used to output a timer underflow signal to external devices from among P10 through P13 by writing "1" to the corresponding bit, CFP10 through CFP13. P10 through P13 correspond to timers 0 through 3, respectively. If "0" is written to CFP1x, the pin is set for an I/O port.

At cold start, CFP1x is set to "0" (I/O port). At hot start, the bit retains its state from prior to the initial reset.

IOC13–IOC10: P1[3:0] port I/O control (D[3:0]) / P1 I/O control register (0x402D6)

Sets input or output mode for P10 through P13.

Write "1": Output mode

Write "0": Input mode

Read: Valid

If a pin chosen from among P10 through P13 is used to output an underflow signal, write "1" to the corresponding I/O control bit to set it to output mode. If the pin is set to input mode, even if its CFP1x is set to "1", it functions as the event counter input pin of a 16-bit programmable timer cannot be used to output a timer underflow signal.

At cold start, IOC1x is set to "0" (input mode). At hot start, the bit retains its state from prior to the initial reset.

CFEX1: P10, P11, P13 port extended function (D1) / Port function extension register (0x402DF)

CFEX0: P12, P14 port extended function (D0) / Port function extension register (0x402DF)

Sets whether the function of an I/O-port pin is to be extended.

Write "1": Function-extended pin

Write "0": I/O-port/peripheral-circuit pin

Read: Valid

When CFEX[1:0] is set to "1", the P13–P10 ports function as debug signal output ports. When CFEX[1:0] = "0", the CFP1[3:0] bit becomes effective, so the settings of these bits determine whether the P13–P10 ports function as I/O port s or timer underflow signal output ports.

At cold start, CFEX[1:0] is set to "1" (function-extended pins). At hot start, CFEX[1:0] retains its state from prior to the initial reset.

RLD07–RLD00: Timer 0 reload data (D[7:0]) / 8-bit timer 0 reload data register (0x40161)

RLD17–RLD10: Timer 1 reload data (D[7:0]) / 8-bit timer 1 reload data register (0x40165)

RLD27–RLD20: Timer 2 reload data (D[7:0]) / 8-bit timer 2 reload data register (0x40169)

RLD37–RLD30: Timer 3 reload data (D[7:0]) / 8-bit timer 3 reload data register (0x4016D)

RLD47–RLD40: Timer 4 reload data (D[7:0]) / 8-bit timer 4 reload data register (0x40175)

RLD57–RLD50: Timer 5 reload data (D[7:0]) / 8-bit timer 5 reload data register (0x40179)

Set the initial counter value of each timer.

The reload data set in this register is loaded into each counter, and the counter starts counting down beginning with this data, which is used as the initial count.

There are two cases in which the reload data is loaded into the counter: when data is preset after "1" is written to PSETx, or when data is automatically reloaded upon counter underflow.

At initial reset, RLD is not initialized.

S1C33210 FUNCTION PART

EPSON

B-III-3-13