III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

Trap vectors

The trap vector addresses for each default interrupt factor are set as shown below:

Timer 0 comparison B: 0x0C00078

Timer 0 comparison A: 0x0C0007C

Timer 1 comparison B: 0x0C00088

Timer 1 comparison A: 0x0C0008C

Timer 2 comparison B: 0x0C00098

Timer 2 comparison A: 0x0C0009C

Timer 3 comparison B: 0x0C000A8

Timer 3 comparison A: 0x0C000AC

Timer 4 comparison B: 0x0C000B8

Timer 4 comparison A: 0x0C000BC

Timer 5 comparison B: 0x0C000C8

Timer 5 comparison A: 0x0C000CC

The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137).

Precaution

Serial interface Ch.2 and Ch.3 share interrupt signals with the 16-bit timers. A register setting determined which is used. The initial setting is for use of the 16-bit timers. Refer to Section III-8, "Serial Interface", for details of the settings.

S1C33210 FUNCTION PART

EPSON

B-III-4-11