III PERIPHERAL BLOCK:
The underflow interrupt factor of the timer 0 to 3 can also invoke
The following shows the HSDMA channel number and trigger
|
| Table 3.5 HSDMA Trigger |
Timer | HSDMA channel | Trigger |
Timer 0 | 0 | HSD0S[3:0] (D[3:0]) / HSDMA Ch.0/1 trigger |
Timer 1 | 1 | HSD1S[3:0] (D[7:4]) / HSDMA Ch.0/1 trigger |
Timer 2 | 2 | HSD2S[3:0] (D[3:0]) / HSDMA Ch.2/3 trigger |
Timer 3 | 3 | HSD3S[3:0] (D[7:4]) / HSDMA Ch.2/3 trigger |
For HSDMA to be invoked, the trigger
If the
For details on HSDMA transfer, refer to "HSDMA
Trap vectors
The trap vector addresses for individual underflow interrupt factors are set by default as shown below:
Timer 0 underflow interrupt: 0x0C000D0
Timer 1 underflow interrupt: 0x0C000D4
Timer 2 underflow interrupt: 0x0C000D8
Timer 3 underflow interrupt: 0x0C000DC
The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137).
S1C33210 FUNCTION PART | EPSON |