III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
Register name | Address | Bit | Name | Function |
| Setting |
| Init. | R/W | Remarks | |||
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HDLC residue | 0200332 | – | – |
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| – |
| – | – | 0 when being read. | ||
code register | (HW) | D7 | RCODE7 | HDLC residue code | RCODE[7:0] |
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| Effective bits | X | R | Only valid when | ||
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| D6 | RCODE6 |
| 11111110 |
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| 7 | X |
| RESID = 1 | |
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| D5 | RCODE5 |
| 11111100 |
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| 6 | X |
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| D4 | RCODE4 |
| 11111000 |
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| 5 | X |
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| D3 | RCODE3 |
| 11110000 |
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| 4 | X |
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| D2 | RCODE2 |
| 11100000 |
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| 3 | X |
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| D1 | RCODE1 |
| 11000000 |
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| 2 | X |
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| D0 | RCODE0 |
| 10000000 |
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| 1 | X |
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HDLC transmit | 0200334 | – | – |
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| – |
| – | – | 0 when being read. | ||
status register | (HW) | D7 | TXUE | HDLC Tx underrun/EOM | 1 | Yes |
| 0 | No | X | R |
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| D6 | TXBRDY | HDLC transmit buffer ready | 1 | not Full |
| 0 | Full | X | R |
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| – | – |
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| – |
| – | – | 0 when being read. | ||
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| D0 | TXUDR | HDLC Tx underrun | 1 | Underrun |
| 0 | No underrun | X | R |
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HDLC monitor | 0200336 | – | – |
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| – |
| – | – | 0 when being read. | ||
register | (HW) | D7 | ESINT | HDLC E/S INT monitored | 1 | Request pending |
| 0 | No interrupts | X | R |
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| D6 | SPINT | HDLC Sp INT monitored | 1 | Request pending |
| 0 | No interrupts | X | R |
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| D5 | RXINT | HDLC Rx INT monitored | 1 | Request pending |
| 0 | No interrupts | X | R |
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| D4 | TXINT | HDLC Tx INT monitored | 1 | Request pending |
| 0 | No interrupts | X | R |
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| – | – |
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| – |
| – | – | 0 when being read. | ||
(0x0200004)
These bits specify the divisor for deriving the communications block clock (SCK) signal from the PERICLK clock signal.
Table 10.12 Communications Block Clock (SCK) Frequency
CKD3 | CKD2 | CKD1 | CKD0 | SCK Clock Frequency Divider |
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| Settings |
1 | 1 | 1 | 1 | fout/16 |
1 | 1 | 1 | 0 | fout/15 |
1 | 1 | 0 | 1 | fout/14 |
1 | 1 | 0 | 0 | fout/13 |
1 | 0 | 1 | 1 | fout/12 |
1 | 0 | 1 | 0 | fout/11 |
1 | 0 | 0 | 1 | fout/10 |
1 | 0 | 0 | 0 | fout/9 |
0 | 1 | 1 | 1 | fout/8 |
0 | 1 | 1 | 0 | fout/7 |
0 | 1 | 0 | 1 | fout/6 |
0 | 1 | 0 | 0 | fout/5 |
0 | 0 | 1 | 1 | fout/4 |
0 | 0 | 1 | 0 | fout/3 |
0 | 0 | 0 | 1 | fout/2 |
0 | 0 | 0 | 0 | fout/2 |
fout = PERICLK output frequency
These bits, together with the MSEL external pin input, specify the communications mode and thus configures the I/O pin the I/O signals to match the target mobile device.
| Table 10.13 | Communications Modes | |||
U_OUTCNT(MSEL) |
| MCRS1 |
| MCRS0 | Communications Mode |
1 |
| 1 |
| 1 | PHS communications |
1 |
| 1 |
| 0 | PDC communications |
1 |
| 0 |
| 1 | HDLC communications |
1 |
| 0 |
| 0 | UART communications |
0 |
| X |
| X | Serial IF Ch. 3 (asynchronous) |
S1C33210 FUNCTION PART | EPSON |