8 ELECTRICAL CHARACTERISTICS

DRAM access cycle common characteristics

(Unless otherwise specified: VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85° C)

Item

Symbol

Min.

Max.

Unit

∗

#RAS signal delay time (1)

tRASD1

 

10

ns

 

#RAS signal delay time (2)

tRASD2

 

10

ns

 

#RAS signal pulse width

tRASW

tCYC(2+WC)-10

 

ns

 

#CAS signal delay time (1)

tCASD1

 

10

ns

 

#CAS signal delay time (2)

tCASD2

 

10

ns

 

#CAS signal pulse width

tCASW

tCYC(0.5+WC)-10

 

ns

 

Read signal delay time (3)

tRDD3

 

10

ns

 

Read signal pulse width (2)

tRDW2

tCYC(2+WC)-10

 

ns

 

Write signal delay time (3)

tWRD3

 

10

ns

 

Write signal pulse width (2)

tWRW2

tCYC(2+WC)-10

 

ns

 

DRAM random access cycle and DRAM fast-page cycle

(Unless otherwise specified: VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85° C)

Item

Symbol

Min.

Max.

Unit

∗

Column address access time

tACCF

 

tCYC(1+WC)-25

ns

 

#RAS access time

tRACF

 

tCYC(1.5+WC)-25

ns

 

#CAS access time

tCACF

 

tCYC(0.5+WC)-25

ns

 

EDO DRAM random access cycle and EDO DRAM page cycle

(Unless otherwise specified: VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85° C)

Item

Symbol

Min.

Max.

Unit

∗

Column address access time

tACCE

 

tCYC(1.5+WC)-25

ns

 

#RAS access time

tRACE

 

tCYC(2+WC)-25

ns

 

#CAS access time

tCACE

 

tCYC(1+WC)-20

ns

 

Read data setup time

tRDS2

20

 

ns

 

Burst ROM read cycle

(Unless otherwise specified: VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85° C)

Item

Symbol

Min.

Max.

Unit

∗

Read address access time (2)

tACC2

 

tCYC(1+WC)-25

ns

 

Chip enable access time (2)

tCEAC2

 

tCYC(1+WC)-25

ns

 

Read signal access time (2)

tRDAC2

 

tCYC(0.5+WC)-25

ns

 

Burst address access time

tACCB

 

tCYC(1+WC)-25

ns

 

External bus master and NMI

(Unless otherwise specified: VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85° C)

Item

Symbol

Min.

Max.

Unit

∗

#BUSREQ signal setup time

tBRQS

16

 

ns

 

#BUSREQ signal hold time

tBRQH

0

 

ns

 

#BUSACK signal output delay time

tBAKD

 

10

ns

 

High-impedance → output delay time

tZ2E

 

10

ns

 

Output → high-impedance delay time

tB2Z

 

10

ns

 

#NMI pulse width

tNMIW

30

 

ns

 

Input, Output and I/O port

(Unless otherwise specified: VDD=2.7V to 3.6V, VSS=0V, Ta=-40°C to +85° C)

 

 

Item

Symbol

Min.

Max.

Unit

∗

 

 

Input data setup time

tINPS

20

 

ns

 

 

 

Input data hold time

tINPH

10

 

ns

 

 

 

Output data delay time

tOUTD

 

20

ns

 

 

 

K-port interrupt

SLEEP, HALT2 mode

tKINW

30

 

ns

 

 

 

input pulse width

Others

 

2 ⋅ tCYC

 

ns

 

 

 

 

 

 

 

 

 

 

 

S1C33210 PRODUCT PART

EPSON

A-77